A power amplifier output power control circuit includes a first operational amplifier with a negative input terminal configured to receive a power control signal; a first PMOS transistor with a grid electrode connected to an output terminal of the first operational amplifier, a source electrode connected to an external power source, and a drain electrode grounded via a voltage dividing network; a power amplifier with a power end connected to the drain electrode of the first PMOS transistor, an input terminal configured to access to a signal to be amplified, and an output terminal configured to amplify the signal; and a current sampling circuit configured to produce sampling current after sampling current across the first PMOS transistor and providing a negative feedback signal for the positive input terminal of the first operational amplifier according to the sampling current such that total output power of the power amplifier keeps unchanged.

The present disclosure describes a method and system for linearizing an amplifier using transistor-level dynamic feedback. The method and system enables nonlinear amplifiers to exhibit linear performance using one or more of gain control elements and phase shifters in the feedback path. The disclosed method and system may also allow an amplifier to act as a pre-distorter or a frequency/gain programmable amplifier.

A broadband amplifier assembly is provided that includes a fixed gain amplifier coupled to an adjustable attenuator which is further coupled to a power amplifier. The adjustable attenuator includes a plurality of attenuation cells directly coupled in series between the input and the output of the adjustable attenuator.

An electronic circuit comprising an ACRF comprising an active component, an energy storage unit, an input port and an output port. The electronic circuit comprises a control unit to control the ACRF. A detector detects a short circuit at the input port or the absence of an energy supply at the input port. The control unit controls the ACRF to function as an ACRF if the detector detects a power supply connected to the input port or that there is no short circuit at the input port, and controls the ACRF to stop functioning as an ACRF and to discharge energy from its energy storage unit to its output port if the detector detects a short circuit at the input port or no power supply connected to the input port.

An electronic circuit comprising an ACRF comprising an active component, an energy storage unit, an input port and an output port. The electronic circuit comprises a control unit to control the ACRF. A detector detects a short circuit at the input port or the absence of an energy supply at the input port. The control unit controls the ACRF to function as an ACRF if the detector detects a power supply connected to the input port or that there is no short circuit at the input port, and controls the ACRF to stop functioning as an ACRF and to discharge energy from its energy storage unit to its output port if the detector detects a short circuit at the input port or no power supply connected to the input port.

A power amplifier output power control circuit includes a first operational amplifier with a negative input terminal configured to receive a power control signal; a first PMOS transistor with a grid electrode connected to an output terminal of the first operational amplifier, a source electrode connected to an external power source, and a drain electrode grounded via a voltage dividing network; a power amplifier with a power end connected to the drain electrode of the first PMOS transistor, an input terminal configured to access to a signal to be amplified, and an output terminal configured to amplify the signal; and a current sampling circuit configured to produce sampling current after sampling current across the first PMOS transistor and providing a negative feedback signal for the positive input terminal of the first operational amplifier according to the sampling current such that total output power of the power amplifier keeps unchanged.

A driver that drives an optical device, such as laser diode (LD) and/or optical modulator, is disclosed. The driver includes a variable gain amplifier (VGA) and a post amplifier. The post amplifier amplifies an output of the VGA to a preset amplifier as varying the gain of the VGA. The VGA includes two differential pairs each amplify the input signal oppositely in phases thereof and outputs of the differential pairs are compositely provided to the post amplifier. The gain of the VGA is varied by adjusting contribution of the second differential pair to the output of the VGA.

The present disclosure describes aspects of a fast settling peak detector. In some aspects, a peak detector circuit includes a first transistor having a gate coupled to an input of the circuit at which a signal is received and a drain coupled to a source of a second transistor. Current may flow in the first and second transistors responsive to the signal. The circuit also includes a third transistor having a gate coupled, via a signal-inverting component, to the input of the circuit and a drain coupled to a source of a fourth transistor. Through an inversion of the signal, other current flowing in the third and fourth transistor can reduce or cancel a frequency component of the current in the first and second transistors. In some cases, this precludes a need to filter the frequency component from an output of the circuit.

A variable attenuation device includes: a first variable attenuator configured to receive a first signal through a first input end, attenuate the first signal by an amount of attenuation according to a control voltage, and output the attenuated first signal through a first output end, the first signal being one of a pair of differential signals having a 180-degree phase difference; a second variable attenuator configured to receive a second signal through a second input end, attenuate the second signal by the amount of attenuation according to the control voltage, and output the attenuated second signal through a second output end, the second signal being the other one of the pair of differential signals; a first signal distributer configured to distribute the second signal to the first output end; and a second signal distributer configured to distribute the first signal to the second output end.

Aspects and examples described herein provide a variable gain amplifier circuit and assembly. In one example, a variable gain amplifier circuit includes a signal input, a signal output, and a variable gain amplifier including a plurality of unit cell groups coupled between the signal input and the signal output, the variable gain amplifier configured to provide an adjustable gain to a signal received at the signal input during each of a plurality of amplify modes of the variable gain amplifier, each of the plurality of amplify modes corresponding to at least one unit cell group of the plurality of unit cell groups. A bypass path including a fixed attenuator is coupled in parallel with the variable gain amplifier between the signal input and the signal output to selectively couple the signal input to the signal output through the fixed attenuator during a bypass mode.