In some embodiments, a method for processing an audio signal in an audio processing apparatus is disclosed. The method includes receiving an audio signal and a parameter, the parameter indicating a location of an auditory event boundary. An audio portion between consecutive auditory event boundaries constitutes an auditory event. The method further includes applying a modification to the audio signal based in part on an occurrence of the auditory event. The parameter may be generated by monitoring a characteristic of the audio signal and identifying a change in the characteristic.

In some embodiments, a method for processing an audio signal in an audio processing apparatus is disclosed. The method includes receiving an audio signal and a parameter, the parameter indicating a location of an auditory event boundary. An audio portion between consecutive auditory event boundaries constitutes an auditory event. The method further includes applying a modification to the audio signal based in part on an occurrence of the auditory event. The parameter may be generated by monitoring a characteristic of the audio signal and identifying a change in the characteristic.

Disclosed herein are signal amplifier architectures that provide a plurality of gain modes. Different gain modes can use different paths through the amplifier architecture. Switches that are used to select the path through the amplifier architecture can be configured to also provide targeted impedance in a degeneration block or matrix. The switches that select the gain path are provided in the amplifier architecture and are thus not needed or used in the degeneration block, thereby reducing the size of the package for the amplifier architecture, improving the noise figure (NF), improving impedance matching, and eliminating the need for control logic associated with the degeneration block or matrix.

Attenuators for radio-frequency (RF) applications. In some embodiments, an attenuator circuit can include one or more attenuation blocks arranged in series between an input node and an output node, with each attenuation block including a local bypass path. The attenuator circuit can further include a global bypass path implemented between the input node and the output node. The attenuator circuit can further include a phase compensation circuit configured to compensate for an off-capacitance effect associated with at least one of the global bypass path and the one or more local bypass paths.

An attenuator arrangement comprising at least a first attenuation path configured to couple between a signal processing chain, SPC, and a measurement apparatus; said SPC comprising a first and second SPC terminal, said SPC configured to apply one or both of a gain and phase change on a signal passed between the SPC terminals; said measurement apparatus configured to measure one or both of the gain and the phase change applied by SPC by coupling to and receiving signals from said SPC terminals; wherein one of said first SPC terminal and said second SPC terminal is coupled to the measurement apparatus through said first attenuation path; and wherein the at least first attenuation path of the attenuator arrangement is configured to provide, selectively, for attenuation of the signal to the measurement apparatus to make the signal power of the signals from said SPC terminals more equal.

A circuit for adjusting an amplitude of an analog input signal includes an amplifier configured to receive the analog input signal and to output an analog output signal responsive to the analog input signal and a gain control signal. A gain control signal generator is also configured to receive the analog input signal and to generate the gain control signal responsive to the analog input signal.

An amplification circuit may include an input terminal, an output terminal, a first amplification path and a second amplification path. The first amplification path may include a first transistor and a second transistor cascoded between the input terminal and the output terminal. The second amplification path may include a third transistor coupled between the input terminal and the output terminal. A control terminal of the first transistor and a control terminal of the third transistor are coupled to the input terminal. A first terminal of the second transistor may be coupled to a second terminal of the first transistor. The first amplification path and the second amplification path may be configured to operate independently of each other. A second terminal of the third transistor and a second terminal of the second transistor are coupled to a common node. In the second amplification path, the transistor closest to the common node is a common-source transistor or a common-emitter transistor.

The present disclosure relates to circuitry for providing an output voltage. The circuitry comprises: voltage generator circuitry configured to provide an output voltage to an output node of the circuitry; current limiter circuitry operable to perform current limiting so as to limit a current supplied at the output node of the circuitry; detection circuitry configured to output a detection signal when a load voltage across a load coupled to the output node of the circuitry reaches a target voltage; and delay circuitry configured to receive the detection signal and to output a control signal to deactivate current limiting by the current limiter circuitry after a predetermined delay period after receiving the detection signal.

The present invention discloses a variable gain amplifier circuit having linearity compensation mechanism is provided. A lower amplification transistor of a lower branch of an amplification circuit is controlled by an AC input signal. Upper amplification transistors of an upper branch generate an AC output signal at an amplification output terminal. An amplification control circuit controls the turn-on and turn-off of the upper amplification transistor according to an amplification control voltage. An inductor is electrically coupled between a power supply terminal and the amplification output terminal. In a gain adjustment circuit, each of adjustment control circuits controls the turn-on and turn-off of each of adjustment transistors according to a adjustment control voltage. A first voltage adjustment circuit adjusts an impedance of each of the adjustment transistors to further adjust an AC cross voltage relation between the lower amplification transistor and the upper amplification transistors.

A variable gain amplifier includes a control unit to acquire set gain information related to a setting of a gain, and, on the basis of the set gain information, output a current to a first reference current transistor and a second reference current transistor in such a manner that the sum of the value of a current to the first reference current transistor and the value of a current to the second reference current transistor becomes constant, and output, to a first variable impedance circuit and a second variable impedance circuit, a voltage obtained by multiplying the absolute value of the difference between the value of a current to the first reference current transistor and the value of a current to the second reference current transistor by a coefficient.