A method for fabricating a device having a cavity, includes: obtaining a device wafer including a first substrate and a device structure formed on the first substrate, depositing a first dielectric layer on the device wafer, etching the first dielectric layer to expose at least a part of the device structure and a part of the first substrate, depositing, after the etching, a second dielectric layer on the device wafer and the first dielectric layer, performing a surface treatment on a surface of the second dielectric layer, obtaining a second substrate, and bonding the second substrate with the second dielectric layer on the device wafer, thereby forming the cavity between the second substrate and the device wafer.

The present invention includes a method for creating a system in a package with integrated lumped element devices is system-in-package (SiP) or in photo-definable glass, comprising: masking a design layout comprising one or more electrical components on or in a photosensitive glass substrate; activating the photosensitive glass substrate, heating and cooling to make the crystalline material to form a glass-crystalline substrate; etching the glass-crystalline substrate; and depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate on the surface of the photodefinable glass, wherein the integrated lumped element devices reduces the parasitic noise and losses by at least 25% from a package lumped element device mount to a system-in-package (SiP) in or on photo-definable glass when compared to an equivalent surface mounted device.

The present invention includes a method for creating a system in a package with integrated lumped element devices is system-in-package (SiP) or in photo-definable glass, comprising: masking a design layout comprising one or more electrical components on or in a photosensitive glass substrate; activating the photosensitive glass substrate, heating and cooling to make the crystalline material to form a glass-crystalline substrate; etching the glass-crystalline substrate; and depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate on the surface of the photodefinable glass, wherein the integrated lumped element devices reduces the parasitic noise and losses by at least 25% from a package lumped element device mount to a system-in-package (SiP) in or on photo-definable glass when compared to an equivalent surface mounted device.

A power splitter for use in an amplifier (e.g., a Doherty amplifier) includes an input terminal, and first and second output terminals. The input terminal is configured to receive an input RF signal, the first output terminal is configured to produce a first RF output signal, and the second output terminal is configured to produce a second RF output signal. The power splitter also includes a first capacitance electrically coupled between the input terminal and the first output terminal, a second capacitance electrically coupled between the input terminal and the second output terminal, a first inductance electrically coupled between the input terminal and a ground reference node, a second inductance electrically coupled between the first output terminal and the ground reference node, a third inductance electrically coupled between the second output terminal and the ground reference node, and a resistance electrically coupled between the first and second output terminals.

A multilayer filter may include a plurality of dielectric layers stacked in a Z-direction. A first conductive layer may overlie one of the dielectric layers, and a second conductive layer may overlie another of the dielectric layers and be spaced apart from the first conductive layer in the Z-direction. A first via may be connected with the second conductive layer at a first location. A second via may be connected with the second conductive layer at a second location that is spaced apart in a first direction from the first location. The first conductive layer may overlap the second conductive layer at an overlapping area to form a capacitor. At least a portion of the overlapping area may be located between the first location and the second location in the first direction. The second conductive layer may be free of via connections that intersect the overlapping area.

A multilayer filter may include a plurality of dielectric layers stacked in a Z-direction. A first conductive layer may overlie one of the dielectric layers, and a second conductive layer may overlie another of the dielectric layers and be spaced apart from the first conductive layer in the Z-direction. A first via may be connected with the second conductive layer at a first location. A second via may be connected with the second conductive layer at a second location that is spaced apart in a first direction from the first location. The first conductive layer may overlap the second conductive layer at an overlapping area to form a capacitor. At least a portion of the overlapping area may be located between the first location and the second location in the first direction. The second conductive layer may be free of via connections that intersect the overlapping area.

Disclosed are devices and methods for fabricating devices. A device can include a passive portion having at least one metal insulator metal (MIM) capacitor and at least one 2-dimensional (2D) inductor. The device further includes a substrate and the passive portion is formed on the substrate. A magnetic core is embedded in the substrate. A 3-dimensional (3D) inductor is also included having windings formed at least in part in the substrate and at least a portion of the windings being formed around the magnetic core.

This disclosure is related to integrating optoelectronics microdevices into a system substrate for efficient and durable electrical bonding between two substrates at low temperature. 2D nanostructures and 3D scaffolds may create interlocking structures for improved bonding properties. Addition of nanoparticles into the structure creates high surface area for better conduction. Application of curing agents before or after alignment of micro devices and receiving substrates further assists with formation of strong bonds.

A filter module for reducing differential and common mode electrical noise may include at least a first electrically conductive busbar and a second electrically conductive busbar spaced apart from the first busbar, an at least partially electrically conductive housing at least partially enclosing the first busbar and the second busbar, at least a first common mode choke and a second common mode choke arranged in the housing and spaced apart from each other, at least a first bypass capacitor electrically connected to the first busbar and the second bus bar, at least a second bypass capacitor electrically connected to the first busbar and a midpoint, and at least a third bypass capacitor electrically connected to the second busbar and the midpoint.

A filter module for reducing differential and common mode electrical noise may include at least a first electrically conductive busbar and a second electrically conductive busbar spaced apart from the first busbar, an at least partially electrically conductive housing at least partially enclosing the first busbar and the second busbar, at least a first common mode choke and a second common mode choke arranged in the housing and spaced apart from each other, at least a first bypass capacitor electrically connected to the first busbar and the second bus bar, at least a second bypass capacitor electrically connected to the first busbar and a midpoint, and at least a third bypass capacitor electrically connected to the second busbar and the midpoint.