The present invention provides a chip component that achieves outstanding LC characteristics. The present invention provides a chip component (1), including: a substrate (12); an inorganic insulating layer (13), formed on the substrate (12); an organic insulating layer (14), formed on the inorganic insulating layer (13); and an LC circuit (6), including a first capacitor (C1) formed in the inorganic insulating layer (13), and a first inductor (L1) formed, in a manner of being electrically connected to the first capacitor (C1), in the organic insulating layer (14).

Aspects of this disclosure relate to a method of manufacturing a packaged acoustic wave component with two acoustic wave devices interconnected by a thermally conductive frame. The method includes providing a first acoustic wave device having a multi-layer piezoelectric substrate structure with a first piezoelectric layer disposed over a first support layer and an interdigital transducer electrode. The method further includes stacking the first acoustic wave device relative to a second acoustic wave device such that a thermally conductive frame extends between the first acoustic wave device and the second acoustic wave device. The thermally conductive frame provides a thermal path for heat dissipation from the first acoustic wave device to the second acoustic wave device.

A phase shifter includes: a first transistor including a first source and a first drain; a second transistor including a second source and a second drain; a first inductor connected with the first source and the first drain, connected in parallel with the first transistor, and including a first body part having an interrupted part, and a first connection part formed at the interrupted part; a second inductor connected with the second source and the second drain, connected in parallel with the second transistor, and including a second body part having an interrupted part, and a second connection part formed at the interrupted part; an inspection drain terminal connected with the first drain and the second drain; and an inspection source terminal connected with the first source and the second source.

A phase shifter includes: a first transistor including a first source and a first drain; a second transistor including a second source and a second drain; a first inductor connected with the first source and the first drain, connected in parallel with the first transistor, and including a first body part having an interrupted part, and a first connection part formed at the interrupted part; a second inductor connected with the second source and the second drain, connected in parallel with the second transistor, and including a second body part having an interrupted part, and a second connection part formed at the interrupted part; an inspection drain terminal connected with the first drain and the second drain; and an inspection source terminal connected with the first source and the second source.

A multilayer circuit board with an LC resonant circuit that has an electronic component package including the multilayer circuit board with the LC resonant circuit are provided. The multilayer circuit board with the LC resonant circuit configured by alternately laminating conductive layers and insulating resin layers on both sides of a core substrate includes a first set of wiring lines, a set of vias, and a second set of wiring lines. The first set of wiring lines configures both ends of the LC resonant circuit and is formed in a first one of the conductive layers. The set of vias extends through the insulating resin layers. The second set of wiring lines is connected to an input/output terminal of the LC resonant circuit and is formed in a second one of the conductive layers. The first set of wiring lines is connected to the second set of wiring lines.

A circuit board has a glass core in which a through hole is formed, and a conductor pattern is formed on an inner peripheral wall of the through hole and a surface of the glass core to form a circuit element including a solenoid coil element and a capacitor element. Accordingly, a low-cost and compact circuit board capable of supporting high-capacity communication for thin mobile communication devices such as smartphones can be provided. Since the circuit board can be electrically connected to at least one of the electronic components such as a switch, an amplifier, and a filter via one terminal, and can be electrically connected to a mother board via another terminal, it has integrated functions, and can be suitably used for thin mobile communication devices such as smartphones.

A high frequency multilayer filter may include a plurality of dielectric layers and a signal path having an input and an output. The multilayer filter may include an inductor including a conductive layer formed over a first dielectric layer. The inductor may be electrically connected at a first location with the signal path and electrically connected at a second location with at least one of the signal path or a ground. The multilayer filter may include a capacitor including a first electrode and a second electrode that is separated from the first electrode by a second dielectric layer. The multilayer filter has a characteristic frequency that is greater than about 6 GHz.

A high frequency multilayer filter may include a plurality of dielectric layers and a signal path having an input and an output. The multilayer filter may include an inductor including a conductive layer formed over a first dielectric layer. The inductor may be electrically connected at a first location with the signal path and electrically connected at a second location with at least one of the signal path or a ground. The multilayer filter may include a capacitor including a first electrode and a second electrode that is separated from the first electrode by a second dielectric layer. The multilayer filter has a characteristic frequency that is greater than about 6 GHz.

A high peak bandwidth I/O channel embedded within a multilayer surface interface that forms the bus circuitry electrically interfacing the output or input port on a first semiconductor die with the input or output port on a second semiconductor die.

A high peak bandwidth I/O channel embedded within a multilayer surface interface that forms the bus circuitry electrically interfacing the output or input port on a first semiconductor die with the input or output port on a second semiconductor die.