RC architectures are provided that include a substrate provided with a capacitor having a thin-film top electrode portion at a surface of the substrate on one side thereof. The resistance provided in series with the capacitor is controlled by providing a contact plate, spaced from the thin-film top electrode portion, and a set of plural bridging contacts extending between, and electrically interconnecting, the thin-film top electrode portion and the contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. The capacitor can be a three-dimensional capacitor and contacts are then provided on respective first and second sides of the substrate, which face each other in the thickness direction of the substrate.

RC architectures are provided that include a substrate provided with a capacitor having a thin-film top electrode portion at a surface of the substrate on one side thereof. The resistance provided in series with the capacitor is controlled by providing a contact plate, spaced from the thin-film top electrode portion, and a set of plural bridging contacts extending between, and electrically interconnecting, the thin-film top electrode portion and the contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. The capacitor can be a three-dimensional capacitor and contacts are then provided on respective first and second sides of the substrate, which face each other in the thickness direction of the substrate.

A balun and a method for manufacturing the same are disclosed. According to an embodiment, the balun comprises a substrate, and a first and a second coplanar waveguide (CPW) couplers which are disposed on the substrate and cascaded with each other. Each CPW coupler comprises two first ground planes disposed on a first side of the substrate, a first microstrip line and at least two second microstrip lines which are disposed on the first side of the substrate between the two first ground planes, and at least one third microstrip line that is disposed on an opposite side of the substrate. The first microstrip line and the at least two second microstrip lines can be coupled with each other by electromagnetic coupling. The at least one third microstrip line electrically connects the at least two second microstrip lines with each other by via-holes.

A balun and a method for manufacturing the same are disclosed. According to an embodiment, the balun comprises a substrate, and a first and a second coplanar waveguide (CPW) couplers which are disposed on the substrate and cascaded with each other. Each CPW coupler comprises two first ground planes disposed on a first side of the substrate, a first microstrip line and at least two second microstrip lines which are disposed on the first side of the substrate between the two first ground planes, and at least one third microstrip line that is disposed on an opposite side of the substrate. The first microstrip line and the at least two second microstrip lines can be coupled with each other by electromagnetic coupling. The at least one third microstrip line electrically connects the at least two second microstrip lines with each other by via-holes.

A circuit board includes a glass substrate having a first surface and a second surface facing away from the first surface; a first coil wiring pattern formed on the first surface and a second coil wiring pattern formed on the second surface, the first and second coil wiring patterns constituting part of a coil; a through hole extending through a predetermined portion of the glass substrate from an end of the first coil wiring pattern to an end of the second coil wiring pattern; a through hole inner conductive surface formed on the inner side of the through hole, the first and second coil wiring patterns and the through hole inner conductive surface constituting the coil wound around a direction perpendicular to an axis of the through hole and to a direction in which the first and second coil wiring patterns extend.

A method of designing a microwave filter using a computerized filter optimizer, comprises generating a filter circuit design in process (DIP) comprising a plurality of circuit elements having a plurality of resonant elements and one or more non-resonant elements, optimizing the DIP by inputting the DIP into the computerized filter optimizer, determining that one of the plurality of circuit elements in the DIP is insignificant, removing the one insignificant circuit element from the DIP, deriving a final filter circuit design from the DIP, and manufacturing the microwave filter based on the final filter circuit design.

An improved filter for high frequency, such as 5G wireless communication, may include inductor-Q improvement and reduced die-size with a hybrid 3D-inductor integration. In some examples, the inductors may be formed using an IPD and a fan-out package. For instance, a first multilayer substrate comprises a plurality of metal insulator metal (MIM) capacitors formed using various layers (e.g., M1 and M2) and a first portion of the 3D inductors, and a second multilayer substrate comprises at least a second portion of the 3D inductors. The 3D inductors may be electrically coupled to the MIM capacitors to form at least one filter network.

A high frequency multilayer filter may include a plurality of dielectric layers and a signal path having an input and an output. The multilayer filter may include an inductor including a conductive layer formed over a first dielectric layer. The inductor may be electrically connected at a first location with the signal path and electrically connected at a second location with at least one of the signal path or a ground. The multilayer filter may include a capacitor including a first electrode and a second electrode that is separated from the first electrode by a second dielectric layer. The multilayer filter has a characteristic frequency that is greater than about 6 GHz.

A high frequency multilayer filter may include a plurality of dielectric layers and a signal path having an input and an output. The multilayer filter may include an inductor including a conductive layer formed over a first dielectric layer. The inductor may be electrically connected at a first location with the signal path and electrically connected at a second location with at least one of the signal path or a ground. The multilayer filter may include a capacitor including a first electrode and a second electrode that is separated from the first electrode by a second dielectric layer. The multilayer filter has a characteristic frequency that is greater than about 6 GHz.

A power splitter for use in an amplifier (e.g., a Doherty amplifier) includes an input terminal, and first and second output terminals. The input terminal is configured to receive an input RF signal, the first output terminal is configured to produce a first RF output signal, and the second output terminal is configured to produce a second RF output signal. The power splitter also includes a first capacitance electrically coupled between the input terminal and the first output terminal, a second capacitance electrically coupled between the input terminal and the second output terminal, a first inductance electrically coupled between the input terminal and a ground reference node, a second inductance electrically coupled between the first output terminal and the ground reference node, a third inductance electrically coupled between the second output terminal and the ground reference node, and a resistance electrically coupled between the first and second output terminals.