A signal processing device has a first discrete time analog signal processing section, which has an input, an output, a plurality of charge storage elements, and plurality of switch elements coupling the charge storage elements. The device has a controller coupled to the first signal processing section configured to couple different subsets of the charge elements of the first signal processing section in successive operating phases to apply a signal processing function to an analog signal presented at the input of the first signal processing section and provide a result of the applying of the signal processing function as an analog signal to the output of first signal processing section. The signal processing function of the first signal processing section comprises a combination of a filtering function operating at a first sampling rate and one or more modulation functions operating at corresponding modulation rates lower than the first sampling rate.

A signal processing device has a first discrete time analog signal processing section, which has an input, an output, a plurality of charge storage elements, and plurality of switch elements coupling the charge storage elements. The device has a controller coupled to the first signal processing section configured to couple different subsets of the charge elements of the first signal processing section in successive operating phases to apply a signal processing function to an analog signal presented at the input of the first signal processing section and provide a result of the applying of the signal processing function as an analog signal to the output of first signal processing section. The signal processing function of the first signal processing section comprises a combination of a filtering function operating at a first sampling rate and one or more modulation functions operating at corresponding modulation rates lower than the first sampling rate.

A discrete time filter, DTF, is described that comprises a summing node; N parallel branches, each branch having a set of input unit sampling capacitances where each unit sampling capacitance is independently selectively coupleable to the summing node; and an output capacitance connected to the summing node. The output capacitance has a value equal to a sum of the sampling capacitances that are to be selectively connected to the summing node; and the discrete time filter further comprises an inductance connected between the summing node and the output capacitance.

A discrete time filter, DTF, is described that comprises a summing node; N parallel branches, each branch having a set of input unit sampling capacitances where each unit sampling capacitance is independently selectively coupleable to the summing node; and an output capacitance connected to the summing node. The output capacitance has a value equal to a sum of the sampling capacitances that are to be selectively connected to the summing node; and the discrete time filter further comprises an inductance connected between the summing node and the output capacitance.

There is provided a communication receiver comprising: an input for receiving a radio frequency, RF, input signal; and at least one finite impulse response, FIR, discrete time filter, DTF. The at least one FIR DTF comprises: an input circuit comprising an input port for sampling the RF input signal at a sampling frequency that is comparable to the input RF input signal; and N parallel branches, each branch having a set of input unit sampling capacitances, where each unit sampling capacitance is independently selectively coupleable to an output summing node. The input circuit is configured to convert an equivalent input impedance of the at least one FIR DTF around the sampling frequency to a real impedance.

In at least one embodiment, a system comprising a first circuit and a second circuit is provided. The first circuit includes a first filter filtering a first input signal and generating a first filtered output signal. The first circuit includes a first comparator comparing the first filtered output signal to a first threshold value and providing a first output signal indicative of a failure condition to one or more first processors. The second circuit includes a second filter filtering the first input signal and generating a second filtered output signal to filter the first input signal in less time than the first filter filtering the first input signal. The second circuit includes a second comparator comparing the second filtered output signal to a second threshold value and providing a second output signal indicative of the failure condition to one or more second processors.

In at least one embodiment, a system comprising a first circuit and a second circuit is provided. The first circuit includes a first filter filtering a first input signal and generating a first filtered output signal. The first circuit includes a first comparator comparing the first filtered output signal to a first threshold value and providing a first output signal indicative of a failure condition to one or more first processors. The second circuit includes a second filter filtering the first input signal and generating a second filtered output signal to filter the first input signal in less time than the first filter filtering the first input signal. The second circuit includes a second comparator comparing the second filtered output signal to a second threshold value and providing a second output signal indicative of the failure condition to one or more second processors.

In at least one embodiment, a system comprising a first circuit and a second circuit is provided. The first circuit includes a first filter filtering a first input signal and generating a first filtered output signal. The first circuit includes a first comparator comparing the first filtered output signal to a first threshold value and providing a first output signal indicative of a failure condition to one or more first processors. The second circuit includes a second filter filtering the first input signal and generating a second filtered output signal to filter the first input signal in less time than the first filter filtering the first input signal. The second circuit includes a second comparator comparing the second filtered output signal to a second threshold value and providing a second output signal indicative of the failure condition to one or more second processors.

An electronic device includes a first resonator electrode and a second resonator electrode in an interconnect stack over a semiconductor substrate. The first resonator electrode includes a first lower resonator electrode, a first upper resonator electrode and a first plurality of vias between the first lower resonator electrode and the first upper resonator electrode. The second resonator electrode includes a second lower resonator electrode, a second upper resonator electrode, and a second plurality of vias between the second lower resonator electrode and the second upper resonator electrode. A cavity in the interconnect stack is bounded by the first resonator electrode and the second resonator electrode. An electron emitter extends from the semiconductor surface between the first and second resonator electrodes and is configured to direct electrons into the cavity. The electronic device may be operated to produce short wavelength radiation, e.g. x-rays.