A filter device includes: delay units serially connected to delay an input signal and output a delayed signal; multiplication units multiplying the delayed signal by a filter coefficient based on a predetermined value and a multiplying factor adjustment value; a coefficient adjustment unit that, when a multiplication result obtained by multiplying the predetermined value by the multiplying factor adjustment value exceeds a maximum value of a filter-coefficient representation range, divides the multiplication result exceeding the maximum value by the maximum value, and outputs a quotient of division as a coefficient adjustment value; a signal conversion unit outputting a signal obtained by adding after-filter-coefficient-multiplication signals outputted by the multiplication units and an adjusted signal obtained by adjusting a corresponding delayed signal using the coefficient adjustment value; and a division unit generating an output signal by dividing the signal outputted by the signal conversion unit by the multiplying factor adjustment value.

This disclosure relates to a system for mitigating distortion in a signal, including a plurality of bit-cells, a calculation circuit configured to determine a bit-cell population that is available to be activated for a given clock cycle, a dynamic element matching network configured to activate a subset of bit-cells of the bit-cell population, and a controller configured to control a pattern of activation of the subset of bit-cells of the bit-cell population.

This disclosure relates to a system for mitigating distortion in a signal, including a first calculation circuit configured to determine a bit-cell population available to be activated of a plurality of bit-cells based on a signal strength of an input signal, a second calculation circuit configured to determine a number of bit-cells to be activated based on the signal strength of the input signal, the number of bit-cells to be activated being less than or equal to the bit-cell population, a variable-width dynamic element matching network (variable DEM) configured to activate a first subset of bit-cells of the bit-cell population based on the number of bit-cells to be activated, and one or more fixed-width dynamic element matching networks (fixed DEMs) configured to activate a second subset of bit-cells of the bit-cell population based on the number of bit-cells to be activated.

A radio frequency (RF) unit and a method for RF isolation. The RF unit includes first and second RF couplers, an RF filter, and an RF canceler connected in parallel with the RF filter. The first RF coupler is configured to receive an input signal. The RF filter is configured to receive a first portion of the input signal from the first RF coupler and attenuate frequencies outside of a passband of the RF filter from the first portion of the input signal. The RF canceler is configured to receive a second portion of the input signal from the first RF coupler and generate a cancellation signal from the second portion of the input signal based on a target frequency band of the RF canceler. The second RF coupler is configured to combine the cancellation signal with an output of the RF filter to generate an output signal.

An apparatus for shifting a digital signal having a first sample rate by a shift time to provide a shifted signal having a second sample rate is provided. The apparatus includes a sample rate converter configured to provide a value of an interpolated signal at a compensated sample time as a sample of the shifted signal, the interpolated signal being based on the digital signal. The sample rate converter is configured to modify a time interval between a sample time of the digital signal and the compensated sample time based on the shift time.

A phase shifter for altering the phase of a radio frequency signal is disclosed herein. A Lange coupler is used having reflective ports that are coupled to artificial transmission lines. The artificial transmission lines provide a reflection transmission path, the length of which can be determined by digital control lines. Transistors placed along the length of the central trace provide independent paths to ground that serve to shorten the electrical length of the ATL. Accordingly, by selectively turning the transistors on/off, the electrical length of the ATL can be selected and thus the amount of phase delay introduced by the phase shifter.

Systems and methods are disclosed for manually and programmatically remediating websites to thereby facilitate website navigation by people with diverse abilities. For example, an administrator portal is provided for simplified, form-based creation and deployment of remediation code, and a machine learning system is utilized to create and suggest remediations based on past remediation history. Voice command systems and portable document format (PDF) remediation techniques are also provided for improving the accessibility of such websites.

Methods and devices are described for reducing the audible effect of pre-responses in an audio signal. The pre-responses are effectively delayed by employing a digital non-minimum-phase filter, which includes a zero lying outside the unit circle in its z-transform response. This zero is not paired with another zero at a reciprocal position inside the unit circle, as this would linearise the phase modification. The filtering can introduce a greater group delay at the pre-response frequency than at a low frequency, such as 500 Hz or even 0 Hz. The technique can be used to reduce pre-responses in an existing audio signal and also to pre-empt pre-responses that would be introduced to the audio signal by subsequent processing.

Provided is a signal processing system including: an adaptive decimation filter apparatus which has a decimation filter which outputs an output signal obtained by down-sampling an input signal, and an aliasing noise detection unit which detects a magnitude of aliasing noise, which is folded back to a frequency lower than a Nyquist frequency in the output signal of the decimation filter by the down-sampling; and a signal processing apparatus which has a filter control unit which adjusts an order of the decimation filter on the basis of the magnitude of the aliasing noise, and an adaptive filter unit which performs filter processing on the output signal of the decimation filter.

Provided is a signal processing system including: an adaptive decimation filter apparatus which has a decimation filter which outputs an output signal obtained by down-sampling an input signal, and a filter control unit which outputs an adjustment signal which adjusts an order of the decimation filter on the basis of a characteristic of the input signal; and a signal processing apparatus which performs signal processing, which corresponds to the adjustment signal, on the output signal of the decimation filter.