An apparatus comprises: a first circuitry to charge first and second capacitors to a predetermined voltage level; a second circuitry to discharge the first capacitor through a diode at a first time; a third circuitry to discharge the second capacitor through the diode at a second time, wherein the second time is greater than the first time; a comparator to compare a first voltage of the first capacitor with a second voltage of the second capacitor; and logic to adjust a scaling factor applied to the second voltage according to an output of the comparator.

This disclosure describes systems, methods, and apparatus for a digital-to-analog (DAC) converter, that can be part of a variable capacitor and/or a match network. The DAC can include a digital input, an analog output, N contributors (e.g., switched capacitors), and an interconnect topology connecting the N contributors, generating a sum of their contributions (e.g., sum of capacitances), and providing the sum to the analog output. The N contributors can form a sub-binary sequence when their contributions to the sum are ordered by average contribution. Also, the gap size between a maximum contribution of one contributor, and a minimum contribution of a subsequent contributor, is less than D, where D is less than or equal to two time a maximum contribution of the first or smallest of the N contributors.

The present disclosure relates to a switch capacitor converter with high efficiency and a small size. The converter according to one aspect of the present disclosure is provided for receiving an input voltage through an input terminal and supplying an output voltage through an output terminal, the converter comprising: a first capacitor; a second capacitor; a third capacitor; and a switch network for changing a connection relationship between the input terminal, the output terminal, the first capacitor, the second capacitor, and the third capacitor. A ratio of the input voltage to the output voltage implemented in the converter is selectable from 4:1, 3:1, or 2:1 depending on an operation of the switch network.

A transceiver device includes a digital baseband circuit, a first circuit portion, and a second circuit portion. The digital baseband circuit is configured to analyze power of an input signal, in order to generate a first control signal and a second control signal. The first circuit portion has a first gain, and is configured to be selected according to the first control signal to process the input signal to generate output signals. The second circuit portion has a second gain higher than the first gain, and is configured to be selected according to the second control signal to process the input signal to generate the output signals. The first circuit portion includes an N-way filter circuit, and the N-way filter circuit is configured to modulate the input signal according to first oscillating signals to perform a filtering operation.

Multipath filters are provided herein. In certain configurations, a multipath filter includes multiple filter paths or circuit branches that are electrically connected in parallel with one another between an input terminal and an output terminal. The input terminal receives an input signal, and each filter circuit branch includes a double-in double-switched (DIDS) downconverter that downconverts the input signal with two different clock signal phases to generate a downconverted signal. Each filter circuit branch further includes a filter network that generates a filtered signal by filtering the downconverted signal and an upconverter that upconverts the filtered signal to generate a branch output signal. Additionally, the branch output signals from the filter circuit branches are combined to generate an output signal at the output terminal.

This disclosure describes systems, methods, and apparatus for a digital-to-analog (DAC) converter, that can be part of a variable capacitor and/or a match network. The DAC can include a digital input, an analog output, N contributors (e.g., switched capacitors), and an interconnect topology connecting the N contributors, generating a sum of their contributions (e.g., sum of capacitances), and providing the sum to the analog output. The N contributors can form a sub-binary sequence when their contributions to the sum are ordered by average contribution. Also, the gap size between a maximum contribution of one contributor, and a minimum contribution of a subsequent contributor, is less than D, where D is less than or equal to two time a maximum contribution of the first or smallest of the N contributors.

An aspect includes a filtering method including operating a first filter to filter a first input signal to generate a first output signal; operating a second filter to filter a second input signal to generate a second output signal; and merging at least a portion of the second filter with the first filter to filter a third input signal to generate a third output signal. Another aspect includes a filtering method including operating switching devices to configure a filter with a first set of pole(s); filtering a first input signal to generate a first output signal with the filter configured with the first set of pole(s); operating the switching devices to configure the filter with a second set of poles; and filtering a second input signal to generate a second output signal with the filter configured with the second set of poles.

An integrator circuit includes: an operational amplifier; a first capacitor coupled to an input of the operational amplifier; a second capacitor coupled in parallel to the first capacitor so that a first terminal of the first capacitor is configured to be electrically coupled to a first terminal of the second capacitor by a first switch; and a second switch configured to electrically couple the first terminal of the second capacitor to a second terminal of the first capacitor.

A filter circuit includes a filter having an input and an output at which an output of the filter is provided, a step detector coupled to receive an input signal at the input of the filter and configured to detect a predetermined step in the input signal and to assert a bypass signal in response to detection of the predetermined step. A logic circuit is responsive to the bypass signal and configured to cause the input signal to be coupled to the output of the filter without filtering when the bypass signal is asserted.

A near field radio-frequency identification (RFID) probe includes a probe tip comprising a resonant coil configured to communicate with an RFID compatible device at a predetermined resonant frequency. The near field RFID probe further includes a plurality of switch capacitor networks each comprising a capacitor and an RF switch, wherein switching the plurality of switch capacitor networks changes the capacitance of the resonant coil, thereby changing the resonant frequency of the resonant coil. The near field RFID probe further includes a probe control module configured to adjust the resonant frequency of the resonant coil to maintain the predetermined resonant frequency by switching the switch capacitor networks responsive to detecting that the resonant frequency of the resonant coil has deviated from the predetermined resonant frequency.