Various embodiments relate to an analog-to-digital converter (ADC). The ADC may include a first channel including a first delta-sigma loop filter and a second channel including a second delta-sigma loop filter. Each of the first delta-sigma loop filter and the second delta-sigma loop filter may include a first integrator and a quantizer having an input coupled to an output of the first integrator. Each of the first delta-sigma loop filter and the second delta-sigma loop filter may also include a first summing node having an output coupled to an input of the first integrator, and a feedforward path from an input of the delta sigma loop filter to a first input of the first summing node. Further, each of the first delta-sigma loop filter and the second delta-sigma loop filter may include a first feedback path from an output of the quantizer to a second input of the first summing node.

Apparatus and associated methods relate to a circuit that is configured to keep a comparator input voltage stable. In an illustrative example, the circuit may include a first differential path coupled to a first switched-capacitor network's output, a second differential path coupled to a second switched-capacitor network's output. A comparator may have a first input coupled to the first differential path and a second input coupled to the second differential path. The comparator may be controlled by a clock signal to perform comparison. A first capacitor may be coupled from the clock signal to the first differential signal path and a second capacitor may be coupled from the clock signal to the second differential signal path. By introducing the first capacitor and the second capacitor, the comparator input common-mode may keep stable, and the comparator may be less sensitive to kickback effects.

This disclosure describes systems, methods, and apparatus for a digital-to-analog (DAC) converter, that can be part of a variable capacitor and/or a match network. The DAC can include a digital input, an analog output, N contributors (e.g., switched capacitors), and an interconnect topology connecting the N contributors, generating a sum of their contributions (e.g., sum of capacitances), and providing the sum to the analog output. The N contributors can form a sub-binary sequence when their contributions to the sum are ordered by average contribution. Also, the gap size between a maximum contribution of one contributor, and a minimum contribution of a subsequent contributor, is less than D, where D is less than or equal to two time a maximum contribution of the first or smallest of the N contributors.

A discrete time filter network with an input signal connection and an output signal connection and comprising a capacitor bank with a plurality of history capacitors, and at least one sampling capacitor which operates at a predetermined cycling rate to couple to at least one history capacitor at a time, which history capacitor is selected from the capacitor bank so as to share electrical charge between such selected history capacitor and the sampling capacitor, wherein there is a plurality of sampling capacitors that are provided in the capacitor bank, and the discrete time filter network is provided with at least one switch network comprising a plurality of clock driven switches for making selected cyclical connections between the sampling capacitors and the history capacitors in the capacitor bank at the predetermined cycling rate.

A switched-capacitor integrator is described having the contribution to offset from the charge injection mismatch of switches connected to the summing nodes mitigated by using a switching scheme that conveys basically all the charge injection to the output, thus preventing net offset from being integrated.

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks on-the-fly, e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

A notch filter is controlled synchronously with a chopper to filter out chopping ripple. In one embodiment, the notch filter is coupled to the differential output of the chopper and includes a sampling capacitor, a hold capacitor, and a second set of switches between the sampling capacitor and the hold capacitor. The second set of switches is temporarily closed once per chopper switching cycle to transfer charge from the sampling capacitor to the hold capacitor such that the ripple from the chopper is not transferred to the hold capacitor. The voltage across the hold capacitor may be coupled to any other circuit, such as to the differential inputs of an amplifier.

Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.

A resonator and resonator method are provided. The resonator includes an inductor, a capacitor, and a switch configured to maintain energy in at least one of the inductor and the capacitor for a select period of time and to enable variability of energy in the at least one of the inductor and the capacitor for another period of time, to set a resonating frequency of the inductor and the capacitor.

Systems and methods for converting a capacitance signal into a band-limited voltage signal for improved signal processing are disclosed herein. Such systems can include a capacitance-to-voltage converter configured to convert a capacitive signal from a capacitive device that operates at a mechanical frequency into a raw voltage signal, a clock generator configured to convert the mechanical frequency into one or more clock signals, and a filter component configured to apply a band-pass filter response to the raw voltage signal to convert the raw voltage signal into a band-limited voltage signal. The clock generator can be configured to apply the one or more clock signals to the filter component to drive a first pole and a second pole of the band-pass filter response to track the mechanical frequency of the capacitive device such that the geometric mean of the first pole and the second pole is substantially equal to the mechanical frequency.