A low noise amplifier is provided. The low noise amplifier includes an input port, an output port, an inverter, a plurality of switched-capacitor units and a feedback inductor. The inverter is electrically connected between the input port and the output port. Each of the plural switched-capacitor units is electrically connected with the inverter in parallel and includes a switch and a capacitor connected in series. The feedback inductor is electrically connected with the inverter in parallel.

This disclosure describes systems, methods, and apparatus for a digital-to-analog (DAC) converter, that can be part of a variable capacitor and/or a match network. The DAC can include a digital input, an analog output, N contributors (e.g., switched capacitors), and an interconnect topology connecting the N contributors, generating a sum of their contributions (e.g., sum of capacitances), and providing the sum to the analog output. The N contributors can form a sub-binary sequence when their contributions to the sum are ordered by average contribution. Also, the gap size between a maximum contribution of one contributor, and a minimum contribution of a subsequent contributor, is less than D, where D is less than or equal to two time a maximum contribution of the first or smallest of the N contributors.

A variable capacitor bank includes a conductive housing and a port extending through the housing. An electrical bus is disposed within the conductive housing and coupled to the port. The variable capacitor bank further includes capacitor modules disposed within the housing. Each capacitor module includes a module input electrically coupled to the electrical bus and a switched capacitor branch electrically coupled to the module input, the switched capacitor branch including a capacitor and a switch element in series with the capacitor. In certain implementations, one or more of the capacitor modules may include at least one second switched capacitor branch. The capacitor modules may further include an unswitched, or floor, capacitor that provides a minimum or otherwise known capacitance of the capacitor module. Each capacitor module may further be grounded by being electrically coupled to the conductive housing.

Multipath filters are provided herein. In certain configurations, a multipath filter includes multiple filter paths or circuit branches that are electrically connected in parallel with one another between an input terminal and an output terminal. The input terminal receives an input signal, and each filter circuit branch includes a double-in double-switched (DIDS) downconverter that downconverts the input signal with two different clock signal phases to generate a downconverted signal. Each filter circuit branch further includes a filter network that generates a filtered signal by filtering the downconverted signal and an upconverter that upconverts the filtered signal to generate a branch output signal. Additionally, the branch output signals from the filter circuit branches are combined to generate an output signal at the output terminal.

The present disclosure relates to a head-wearable hearing device which comprises a magnetic inductance antenna having a predetermined resonance period for receipt of wireless data signals and a switched capacitor DC-DC converter configured for converting a DC input voltage into a higher or lower DC output voltage in accordance with a clock signal. The charge pump circuit is configured to charge an output capacitor by output current pulses where the output current pulses at least comprise first and second consecutive output current pulses having a mutual pulse delay corresponding to substantially one-half of the predetermined resonance period of the magnetic inductance antenna.

A variable capacitor bank includes a conductive housing and a port extending through the housing. An electrical bus is disposed within the conductive housing and coupled to the port. The variable capacitor bank further includes capacitor modules disposed within the housing. Each capacitor module includes a module input electrically coupled to the electrical bus and a switched capacitor branch electrically coupled to the module input, the switched capacitor branch including a capacitor and a switch element in series with the capacitor. In certain implementations, one or more of the capacitor modules may include at least one second switched capacitor branch. The capacitor modules may further include an unswitched, or floor, capacitor that provides a minimum or otherwise known capacitance of the capacitor module. Each capacitor module may further be grounded by being electrically coupled to the conductive housing.

A circuit for processing an input-signal voltage, and including an input capacitance coupled between an input node of the circuit and a sense node of a comparator; a reference capacitance coupled to the sense node of the comparator; and a common mode switch coupled between the sense node and a reference node of the comparator. The circuit is configured to have the input capacitance set to a reference input voltage while the common mode switch is closed, and the input node set to the input-signal voltage while the common mode switch is open. The reference capacitance includes a plurality of capacitances, at least one of which is provided as a switched capacitance that is selectively controllable to configure the plurality of capacitances. A switched capacitance controller is configured to control the switched capacitance so as to compensate, at the sense node, a comparator offset voltage.

A system may comprise a high-pass filter having an input for receiving an input signal, an output for generating an output signal, a capacitor coupled between the input and the output, a switched-capacitor resistor coupled between the output and a reference voltage, and control circuitry configured to control the reference voltage to cancel current leakage into a circuit coupled to the output. The input, the output, the capacitor, and the switched-capacitor resistor may be arranged to generate the output signal as a high-pass filtered version of the input signal and the high-pass filter may be configured to operate in a plurality of modes comprising at least a high-impedance mode and a low-impedance mode in which the resistance of the switched-capacitor resistor is significantly smaller than the resistance when in the high-impedance mode. A system may include a plurality of processing paths having a first path configured to generate a first digital signal based on an analog input signal and a second path configured to generate a second digital signal based on the analog input signal, the second path having a high-pass filter for filtering the analog input signal prior to the analog input signal being processed by the remainder of the second path, and the high-pass filter having a corner frequency. Control circuitry may be configured to determine frequency-dependent weighted proportions of the first and second digital signals to be combined into an output digital signal based on a characteristic of the analog input signal. Frequency-dependent weighted proportions may be such that the digital output signal includes spectral content of the first digital signal below the corner frequency to account for spectral content of the second digital signal below the corner frequency being filtered. A system may include an input for receiving an input signal, an output for generating an output signal, a capacitor coupled between the input and the output, a variable resistor coupled to the output and having a plurality of modes including a first mode in which the variable resistor has a first resistance and a second mode in which the variable resistor has a second resistance, and control circuitry configured to determine a difference between the input signal and the output signal and switch between modes of the plurality of modes when the difference is less than a predetermined threshold.

A resonator and resonator method are provided. The resonator includes an inductor, a capacitor, and a switch configured to maintain energy in at least one of the inductor and the capacitor for a select period of time and to enable variability of energy in the at least one of the inductor and the capacitor for another period of time, to set a resonating frequency of the inductor and the capacitor.

A circuit containing a first cascode circuit and a second cascode circuit is proposed. The first circuit and the second cascode circuit are stacked between two power supply terminals. An output signal terminal of the circuit is coupled to a node connecting the first cascode circuit and the second cascode circuit. A first signal path is provided between the first cascode circuit and a common ground terminal and a second signal path is provided between the second cascode circuit and the common ground terminal.