A built-in self-test (BIST) methodology and apparatus provide for testing and calibration of an integrated circuit oscillator circuit topology that uses a one-pin (a single-pin) external resonator. The method employs dedicated test circuitry, also referred to herein as BIST apparatus, for the pass/fail verification of both the active and passive building blocks of the oscillator. At the same time, the methodology ensures accurate calibration and matching of the capacitors using dedicated digital circuitry and algorithms.

A built-in self-test (BIST) methodology and apparatus provide for testing and calibration of an integrated circuit oscillator circuit topology that uses a one-pin (a single-pin) external resonator. The method employs dedicated test circuitry, also referred to herein as BIST apparatus, for the pass/fail verification of both the active and passive building blocks of the oscillator. At the same time, the methodology ensures accurate calibration and matching of the capacitors using dedicated digital circuitry and algorithms.

A built-in self-test (BIST) methodology and apparatus provide for testing and calibration of an integrated circuit oscillator circuit topology that uses a one-pin (a single-pin) external resonator. The method employs dedicated test circuitry, also referred to herein as BIST apparatus, for the pass/fail verification of both the active and passive building blocks of the oscillator. At the same time, the methodology ensures accurate calibration and matching of the capacitors using dedicated digital circuitry and algorithms.

A built-in self-test (BIST) methodology and apparatus provide for testing and calibration of an integrated circuit oscillator circuit topology that uses a one-pin (a single-pin) external resonator. The method employs dedicated test circuitry, also referred to herein as BIST apparatus, for the pass/fail verification of both the active and passive building blocks of the oscillator. At the same time, the methodology ensures accurate calibration and matching of the capacitors using dedicated digital circuitry and algorithms.

A transceiver device includes a pulse generator, an output node, and an internal bus that couples the pulse generator and the output node. The pulse generator is configured to selectively add at least one pulse to an outlet power supply signal conveyed by the internal bus to the output node, wherein the pulse generator includes a bootstrap capacitor with a first side coupled to the internal bus and a second side selectively coupled to at least one current source. A transceiver method includes receiving an inlet power supply signal and providing an outlet power supply signal to an output node, wherein the outlet power supply signal is based on the inlet power supply signal. The transceiver method also includes selectively adding a sync or data pulse to the outlet power supply signal based on a pulse scheme and a bootstrap capacitor coupled to the output node.

A transceiver device includes a pulse generator, an output node, and an internal bus that couples the pulse generator and the output node. The pulse generator is configured to selectively add at least one pulse to an outlet power supply signal conveyed by the internal bus to the output node, wherein the pulse generator includes a bootstrap capacitor with a first side coupled to the internal bus and a second side selectively coupled to at least one current source. A transceiver method includes receiving an inlet power supply signal and providing an outlet power supply signal to an output node, wherein the outlet power supply signal is based on the inlet power supply signal. The transceiver method also includes selectively adding a sync or data pulse to the outlet power supply signal based on a pulse scheme and a bootstrap capacitor coupled to the output node.

An electronic device may include a ramp signal generator suitable for generating a ramp signal having a slope corresponding to an analog gain, and a slope correction circuit suitable for correcting the slope based on a correction code signal.

An electronic device may include a ramp signal generator suitable for generating a ramp signal having a slope corresponding to an analog gain, and a slope correction circuit suitable for correcting the slope based on a correction code signal.

The present technology relates to an image pickup device and an electronic apparatus capable of preventing degradation of the picture quality. A plurality of current sources can be selectively connected to an output terminal for outputting a reference signal having a level that varies, and a plurality of terminating resistors are connected to the output terminal. The terminating resistors that are to supply current of current sources that are connected to the output terminal are connected by a plurality of switches, and current of current sources that are not connected to the output terminal is supplied to the switches. The present technology can be applied, for example, to image pickup devices that perform AD conversion using a reference signal and so forth.

In summary, a switching circuit comprising a high side (HS) switch coupled to the output, a low side (LS) switch comprising a MOSFET coupled to the output, and a slope regulator core coupled to the gate of said low side (LS) switch configured to provide control signals to said slope regulator core. In addition, a method of providing a method of a switch circuit comprising the steps the first step, (a) providing a circuit comprising a low side (LS) switch, a high side (HS) switch, and a slope regulator wherein said slope regulator comprises a fast mode, a slope regulator mode, and a hold mode, the second step (b) activating said slope regulator, the third step (c) choosing a fast mode or a slope regulation mode, the fourth step (d) applying either a fast mode or slope regulation mode; the fifth step (e) evaluating the polarity of the signal, the sixth step (f) toggle signal hold_on if the gate is low or toggle signal hold_off if the gate is high.