An example device includes splitter logic to split an input sample having a predetermined number of bits into a first segment of most significant bits and a second segment of least significant bits. Pulse logic generates a pattern of pulses that correlate to the values of the most significant bits. Edge mover logic determines edge adjustment data based on the values of the least significant bits, the edge adjustment data representing an adjustment to at least one edge in the pattern of pulses. Combiner logic generates an enhanced pulse stream by adjusting at least one edge in the pattern of pulses based on the edge adjustment data.

An example device includes splitter logic to split an input sample having a predetermined number of bits into a first segment of most significant bits and a second segment of least significant bits. Pulse logic generates a pattern of pulses that correlate to the values of the most significant bits. Edge mover logic determines edge adjustment data based on the values of the least significant bits, the edge adjustment data representing an adjustment to at least one edge in the pattern of pulses. Combiner logic generates an enhanced pulse stream by adjusting at least one edge in the pattern of pulses based on the edge adjustment data.

Methods and systems for cyber secure data communications are provided. In some embodiments, a method for transmitting data comprises: performing a marker-based data encoding process to embed a digital watermark into each of a plurality of original data flows to be transmitted to a plurality of receivers; performing a non-orthogonal multiple access process to allocate transmission powers to the plurality of original data flows, such that the plurality of original data flows are simultaneously superposed on a carrier frequency to generate a superposed signal; performing a noise modulation process to modulate the superposed signal to generate a noise-like signal and a reference noise signal; transmitting the noise-like signal and the reference noise signal through orthogonally polarized antennas; and performing a portal-based data integrity analysis process to check whether a receiver in the plurality of receivers is compromised or manipulated.

An example device includes splitter logic to split an input sample having a predetermined number of bits into a first segment of most significant bits and a second segment of least significant bits. Pulse logic generates a pattern of pulses that correlate to the values of the most significant bits. Edge mover logic determines edge adjustment data based on the values of the least significant bits, the edge adjustment data representing an adjustment to at least one edge in the pattern of pulses. Combiner logic generates an enhanced pulse stream by adjusting at least one edge in the pattern of pulses based on the edge adjustment data.

A processor, that may include at least one neural network that comprises at least one leaky spiking neuron; wherein the at least one leaky spiking neuron is configured to directly receive an input pulse density modulation (PDM) signal from a sensor; wherein the input PDM signal represents a detected signal that was detected by the sensor; and wherein the at least one neural network is configured to process the input PDM signal to provide an indication about the detected input signal.

A processor, that may include at least one neural network that comprises at least one leaky spiking neuron; wherein the at least one leaky spiking neuron is configured to directly receive an input pulse density modulation (PDM) signal from a sensor; wherein the input PDM signal represents a detected signal that was detected by the sensor; and wherein the at least one neural network is configured to process the input PDM signal to provide an indication about the detected input signal.

A buck converter device with minimum off-time operation, the device comprising a comparator providing an output signal of a minimum off time, a first amplifier, a p-channel MOSFET whose gate is connected to the output of a first amplifier providing a signal threshold voltage to a positive terminal of a comparator, a second amplifier; and, a second p-channel MOSFET whose gate is connected to the output of a second amplifier providing a signal to a negative terminal of a comparator, and a capacitor element. A capacitor establishes a voltage whose rate of change is proportional to power supply Vdd, establishing a time to charge the capacitor to a threshold voltage proportional to (VddVref)/Vdd, and establishing a minimum off time on the output of a comparator.

Methods and systems for cyber secure data communications are provided. In some embodiments, a method for transmitting data comprises: performing a marker-based data encoding process to embed a digital watermark into each of a plurality of original data flows to be transmitted to a plurality of receivers; performing a non-orthogonal multiple access process to allocate transmission powers to the plurality of original data flows, such that the plurality of original data flows are simultaneously superposed on a carrier frequency to generate a superposed signal; performing a noise modulation process to modulate the superposed signal to generate a noise-like signal and a reference noise signal; transmitting the noise-like signal and the reference noise signal through orthogonally polarized antennas; and performing a portal-based data integrity analysis process to check whether a receiver in the plurality of receivers is compromised or manipulated.

Aspects of the disclosure provide a circuit that includes a clock synchronization circuit. The clock synchronization circuit is configured to determine a sub-cycle offset between a first clock signal and a second clock signal, and select rising/failing edges of the first clock signal and the second clock signal based on the sub-cycle offset for enabling communication between a first clock domain that is operative in response to the first clock signal and a second clock domain that is operative in response to the second clock signal.

A voltage converter can be switched among two or more modes to produce an output voltage tracking a reference voltage that can be of an intermediate level between discrete levels corresponding to the modes. One or more voltages generated from a power supply voltage, such as a battery voltage, can be compared with the reference voltage to determine whether to adjust the mode. The reference voltage can be independent of the power supply voltage. Further, the voltage converter may implement frequency modulation and a pulse skipping mode to improve the efficiency of switching operational states of the voltage converter.