In accordance with embodiments disclosed herein, there is provided systems and methods for on-chip jitter tolerance testing. A receiver component includes a clock data recovery (CDR) logic circuit. The CDR logic circuit includes a controller to receive a phase signal and to output a DCO control signal; jitter injection (JINJ) logic to generate a first jitter signal at a first frequency and a first amplitude; and digitally controlled oscillator (DCO) to receive the first jitter signal applied to the DCO control signal and to output, based on the first jitter signal applied to the DCO control signal, a first DCO clock signal for on-chip jitter tolerance testing.

Methods and systems for cyber secure data communications are provided. In some embodiments, a method for transmitting data comprises: performing a marker-based data encoding process to embed a digital watermark into each of a plurality of original data flows to be transmitted to a plurality of receivers; performing a non-orthogonal multiple access process to allocate transmission powers to the plurality of original data flows, such that the plurality of original data flows are simultaneously superposed on a carrier frequency to generate a superposed signal; performing a noise modulation process to modulate the superposed signal to generate a noise-like signal and a reference noise signal; transmitting the noise-like signal and the reference noise signal through orthogonally polarized antennas; and performing a portal-based data integrity analysis process to check whether a receiver in the plurality of receivers is compromised or manipulated.

This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization circuit. The digital logic circuit can have a plurality of inputs and can include a plurality of logic gates. The polarization circuit can receive a standby signal and a digital input signal comprising a plurality of bits. When the standby signal is deactivated, the polarization circuit can control the plurality of inputs of the digital logic circuit based on the digital input signal. However, when the standby signal is activated the polarization circuit can control the plurality of inputs of the digital logic circuit to a low power state associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the digital logic circuit.

A semiconductor device includes first and second buffers respectively outputting reception data and clock signals; a latch circuit latching the reception data signal in response to the reception clock signal; a delay circuitry delaying the reception clock signal by a set delay time; and a delay control circuitry which searches a first delay time while increasing the set delay time from an initial value; searches a second delay time while increasing the set delay time from the first delay time; searches a third delay time while decreasing the set delay time from the second delay time; and determines an optimum delay time from the first and third delay times. The first and third delay times are determined so that the reception data is stabilized to a first value and the second delay time is determined so that the reception data is stabilized to a second value.

A communication system includes a first radio module and a second radio module. The first radio module includes a tuner communicatively coupled to a reference signal generator that is configured to generate a first reference signal for the tuner. The first radio module further includes a serializer configured to serialize a signal output by the tuner. The second radio module includes a deserializer configured to receive a serialized version of the signal from the serializer of the first radio module and deserialize the serialized version of the signal. The second radio module further includes a second tuner that is communicatively coupled to a clock recovery circuit. The clock recovery circuit is configured to generate a second reference signal for the second tuner based on a deserialized version of the first signal, where the second reference signal is frequency and phase locked to the first reference signal.

The present application provides a non-orthogonal demodulation module, receiving a received signal and the received signal is related to a summation of a plurality of transmitted signals. The plurality of transmitted signals are corresponding to a plurality of frequencies, and the plurality of transmitted signals are not orthogonal to each other. The non-orthogonal demodulation module comprises a mixing-and-integrating unit, configured to perform mixing operations and integrating operations on the received signal respectively at the plurality of frequencies, to generate a plurality of in-phase components and a plurality of quadrature components corresponding to the plurality of frequencies; and a decoding unit, configured to generate at least a decoding matrix, and compute a plurality of energies corresponding to the plurality of transmitted signals according to the at least a decoding matrix, the plurality of in-phase components and the plurality of quadrature components.

The present invention relates to a method and apparatus for channel estimation between a transmitter and a receiver in a wireless communications system. In one arrangement, the method comprises: receiving at the receiver a first sequence of bits representing a first sequence of coded symbols transmitted over the communications channel; decoding the first sequence of coded symbols using maximum-likelihood based decoding including: generating traceback outcomes by tracing backwards the first sequence of bits through a maximum-likelihood based traceback path, the traceback outcomes including a first portion associated with a first traceback depth and a second portion associated with a second traceback depth that is deeper than the first traceback depth; generating a channel estimate of the communications channel based on the first portion of the traceback outcomes; and generating an estimate of at least some information bits coded in the first sequence of coded symbols based on the second portion of the traceback outcomes.

For example, an averaging circuit includes first to third capacitors and a controller. The controller causes a first first-stage average voltage to be applied to a first capacitor, the first first-stage average voltage being an average of a first voltage applied to the first capacitor and a second voltage applied to a second capacitor, causes a second first-stage average voltage to be applied to the second capacitor, the second first-stage average voltage being an average of a third voltage applied to the second capacitor and a fourth voltage applied to a third capacitor, and causes a first second-stage average voltage to be applied to the first capacitor, the first second-stage average voltage being an average of the first and second first-stage average voltages applied to the first and second capacitors.

Methods, systems, devices, and apparatuses are described for phase noise estimation. A transmitting device identifies a phase noise metric associated with a receiving device. The phase noise metric provides an indication of the expected phase noise for the receiving device. The transmitting device selects a plurality of pilot tones adjacent to each other and a plurality of null tones for a transmission to the receiving device based on the phase noise metric. The plurality of null tones may be adjacent to and on both sides of the pilot tones in the frequency domain. The transmitting device identifies its own phase noise metric and select the pilot tones adjacent to each other and plurality of null tones in further consideration of its own phase noise metric. The receiving device may use the pilot tones and plurality of adjacent null tones to determine a phase noise estimation for the transmission.

A method and an apparatus for receiving broadcast signals thereof are disclosed. The apparatus for receiving broadcast signals, the apparatus comprises a receiver to receive the broadcast signals, a demodulator to demodulate the received broadcast signals by an OFDM (Orthogonal Frequency Division Multiplex) scheme, a frame parser to parse a signal frame from the demodulated broadcast signals, wherein the signal frame includes service data corresponding to each of a plurality of physical paths, a time deinterleaver to time deinterleave service data in each physical path by a TI (Time Interleaving) block, wherein the time deinterleaver further performs inserting at least one virtual FEC block into at least one TI block of the service data, wherein each TI block includes a variable number of FEC blocks of the service data, wherein a number of the at least one virtual FEC block is defined based on a maximum number of FEC blocks of a TI block and a decoder to decode the time deinterleaved service data.