The broadcast-signal transmitter according to one embodiment of the present invention includes: an encoder for encoding physical layer pipe (PLP) data, including a base layer and an enhancement layer of a broadcasting service, and signaling information through a SISO, and/or MIMO technique; a frame builder for generating a transmission frame, which includes a preamble having the encoded signaling information and the PLP data and an OFDM generator for modulating and transmitting a broadcast signal including the transmission frame.

A receiving circuit includes a receiver configured to receive a signal, a detector configured to detect arrival of a reception signal based on a signal received by the receiver, a buffer configured to store therein data corresponding to the reception signal, a demodulation processor configured to demodulate data to be supplied, and a controller configured to store the data corresponding to the reception signal in the buffer when the detector does not detect the arrival of the reception signal, and to supply the data stored in the buffer to the demodulation processor when the detector detects the arrival of the reception signal.

An apparatus for wireless communications is disclosed. The apparatus includes a processing system configured to generate a frame having a preamble, a header, and a data payload, wherein the preamble, the header, and the data payload are decodable by a first device when operating according to a first protocol, wherein the preamble and the header are decodable by a second device when operating according to a second protocol, the data payload not being decodable by the second device when operating according to the second protocol; and an interface configured to output the frame for transmission.

According to an embodiment, a circuit package includes a programmable switch component having a plurality of input terminals arranged on the programmable switch component, a plurality of output terminals arranged on the programmable switch component and configured to be coupled to a plurality of amplifiers, and a plurality of switches. Each switch of the plurality of switches is coupled between an input terminal of the plurality of input terminals and an output terminal of the plurality of output terminals. Each switch of the plurality of switches includes a radio frequency (RF) switch and is configured to pass an RF signal when closed. Each input terminal of the plurality of input terminals is coupled to two switches of the plurality of switches.

In an embodiment an envelope detection device includes an input terminal configured to receive an amplitude-modulated radio frequency signal, a first resistive element and a first MOS transistor connected in parallel between the input terminal and a first node configured to receive a reference potential, a first capacitive element connected between a gate of the first MOS transistor and the first node, an envelope detection circuit connected to the input terminal and configured to supply a voltage representative of an envelope of the amplitude-modulated signal and a circuit for controlling the first MOS transistor configured to supply a first current to the gate of the first MOS transistor only when the voltage is smaller than a first threshold and draw a second current from the gate of the first MOS transistor only when the voltage is higher than a second threshold, the second threshold being higher than the first threshold.

A re-sampler comprises: a plurality of multipliers configured to receive an input sample; and a plurality of accumulators coupled to the multipliers and configured to form multiplier-accumulator (MAC) units with the multipliers, wherein the MAC units are configured to: compute partial products from the input sample, accumulate the partial products over clock cycles, and sequentially generate output samples based on the computing and the accumulating. A method comprises: receiving input samples; computing partial products from the input samples; accumulating the partial products over clock cycles; and sequentially generating output samples based on the computing and the accumulating.

A digital broadcasting system and a method of processing data are disclosed, which are robust to error when mobile service data are transmitted. To this end, additional encoding is performed for the mobile service data, whereby it is possible to strongly cope with fast channel change while giving robustness to the mobile service data.

A communication unit receiver comprising: a multi-section analog to digital converter, ADC, configured to receive an analog signal and convert at least a first portion of the analog signal into a digital signal using a first ADC dynamic range. A modem, coupled to the multi-section ADC, is configured to: process the digital signal; determine a signal-to-noise ratio, SNR, for sub-carriers of the analog signal; and output an ADC selection signal to the multi-section ADC that selects a subset of sections of the multi-section ADC, where the selection signal is based at least partly on the determined SNR. Only the subset of sections of the multi-section analog to digital converter, ADC is configured to convert a second portion of the analog signal into a digital signal using a second ADC dynamic range that is less than the first dynamic range.

A beamforming system synchronization architecture is proposed to allow a receiving device to synchronize to a transmitting device in time, frequency, and spatial domain in the most challenging situation with very high pathloss. A periodically configured time-frequency resource blocks in which the transmitting device uses the same beamforming weights for its control beam transmission to the receiving device. A pilot signal for each of the control beams is transmitted in each of the periodically configured time-frequency resource blocks. Pilot symbols are inserted into pilot structures and repeated for L times in each pilot structure. The L repetitions can be implemented by one or more Inverse Fast Fourier Transfers (IFFTs) with corresponding one or more cyclic prefix (CP) lengths.

According to an embodiment, an analog-to-digital converter includes a detection circuit, a first conversion circuit, a second comparator, a delay control circuit, a control circuit. A detection circuit detects a differential time signal corresponding to a delay time by using a comparison signal and a delay comparison signal. A first conversion circuit generates a differential voltage by performing time-to-voltage conversion on the differential time signal. A second comparator generates a digital delay determination signal by comparing the differential voltage and an adjustment target voltage. A delay control circuit generates a delay control signal controlling the delay time in accordance with a delay determination signal. A control circuit generates a control signal by using the delay comparison signal in an analog-to-digital conversion period.