A drive circuit Dr for a switch that reduces a surge voltage caused when a switch SW is switched to an off state. The drive circuit Dr detects, as an on voltage Von, a collector-emitter voltage of the switch SW while the switch SW is in an on state. When the detected on voltage Von is large, the drive circuit Dr sets a resistance value Rd of a discharging resistor 53 when the switch SW is switched to an off state to be larger than the resistance value Rd when the detected on voltage Von is small. More specifically, the drive circuit Dr sets the resistance value Rd to a larger value as the detected on voltage Von is increased.

A multiplexer device includes a plurality of selection circuits and potential setting circuits. The plurality of selection circuits respectively receive a first data signal and a second data signal, and select a corresponding one of the first data signal and the second data signal as an output signal according to the first selection signal. When the second data signal is selected as the output signal, the potential setting circuit sets a potential of a node of a first selection circuit of the plurality of selection circuits to a first voltage. The first selection circuit is configured to receive a first data signal.

A signal detection circuit includes: a first capacitor having a first terminal connected with a first main terminal of a switching element; a second capacitor having a first terminal connected with a second main terminal of the switching element; and a detection circuit having a differential circuit configuration. The detection circuit receives, as input signals, a signal from a second terminal of the first capacitor and a signal from a second terminal of the second capacitor, detects detection target signals based on the input signals. The detection target signals include a signal of the first main terminal of the switching element and a signal of the second main terminal of the switching element.

There is provided a switching apparatus (30,130) comprising: first and second nodes (32,34) operably connectable to a line voltage (44); first and second switching branches (38,40) connected in parallel between the first and second nodes (32,34), the first switching branch (38) including at least one first switching element (46,60); and the second switching branch (40) including a pair of switching assemblies connected in series between the first and second nodes (32,34), the second switching branch (40) further including a junction (48) between the pair of switching assemblies, each switching assembly including at least one second switching element (50), at least one of the switching assemblies further including at least one impedance element (52), wherein the switching apparatus (30,130) further includes a shunt impedance (42) and a third node (36), the shunt impedance (42) arranged to form a permanent electrical connection between the junction (48) and the third node (36), the third node (36) operably connectable to a voltage that is different in magnitude to the line voltage (44), the or each impedance element (52) arranged in the corresponding switching assembly to combine with the shunt impedance (36) so as to define a current path which extends between the corresponding first or second node (32,34) and the third node (36).

A power source selection system can include a primary source line configured to be connected to a primary source having a primary voltage, a backup source line configured to connect to a backup source having a backup voltage, and a voltage divider and limiter connected to the primary source line to receive the primary voltage and to provide an sense signal on a sense line. The system can include a NAND gate connected to the voltage divider and limtier to receive the sense signal. The NAND gate can be configured to provide a gate signal to a gate line based on the sense signal. The system can include a switchover circuit connected to the backup source line and the gate line to receive the backup voltage and the gate signal. The switchover circuit can be configured to output the backup voltage to a switch line in a first state, and to prevent backup voltage to the switch line in a second state. The switchover circuit can be configured to switch between the first state and the second state based on the gate signal. The system can include an ORing circuit connected to the primary source line and to the switch line. The ORing circuit can be configured to select between the primary voltage and backup voltage and to output the selected voltage as the output voltage.

A radio frequency circuit includes a transmit filter for B66-Tx connected to a power amplifier, a transmit filter for B25-Tx connected to a power amplifier, a switch circuit having terminals, a switch circuit having a common terminal and terminals, and a switch circuit having a common terminal and terminals. The terminal is connected to the common terminal, the terminal is connected to the common terminal, the terminal is connected to the transmit filter, and the terminal is connected to the transmit filter. The switch circuit has a smaller stack number than the switch circuit, and the switch circuit has a smaller stack number than the switch circuit.

Techniques regarding quantum gate coupling are provided. For example, one or more embodiments described herein can comprise a method for driving multiple resonator induced phase gates from the same signal control line. The method can comprise controlling quantum gate coupling, via a quantum circuit, by filtering a resonator induced phase gate signal from a signal control line that is multiplexed with a plurality of resonator induced phase gate signals.

Circuits and methods for transmitting high-voltage (HV) static and/or switching signals via a high-voltage (HV) transmission gate controllable via low-voltage (LV) logic are presented. The HV gate includes a biasing circuit for generating a biasing voltage to gates of two series-connected HV transistors. According to one aspect, the biasing voltage is generated through a pull-up device coupled to a HV supply having a voltage level higher than a high voltage of a signal to be transmitted. According to another aspect, the biasing voltage is generated through a LV supply coupled to a diode, and a capacitor coupled between the gates and the sources of the HV transistors. When the gate is activated, the combination of the LV supply coupled to the diode and the capacitor generates a biasing voltage based on a sum of a voltage of the LV supply and an instantaneous voltage level of the signal being transmitted.

A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.

First switches are respectively connected between multiple input terminals and an inverting input of an operational amplifier. Second switches and feedback resistors are respectively sequentially series-connected between an output of the operational amplifier and nodes between the multiple input terminals and the first switches. Third switches are respectively connected between nodes between the second switches and the feedback resistors and an output terminal of an amplification circuit with an analog multiplexer.