An apparatus, a memory device, and a method for storing parameter codes with respect to asymmetric on-die-termination (ODT) are provided. The apparatus is connected to an external device via a signal line, and includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.

Circuits and methods that harvest electrostatic energy from transient on-chip data are described in the Application. In one aspect, a method and inverter circuit harvests electrostatic charge held at its output node at an electric potential comparable to the power supply voltage rail to a common grid/node as the output makes a 1.fwdarw.0 logic transition. This charge harvested at a common grid/node can be used by circuits (described in applications 63/090,169, 63/139,744) to drive 0.fwdarw.1 logic transition at their output nodes at lower energy drain from the on-chip power grid than a conventional CMOS inverter would with similar performance, slew rates at inverter input and output and with similar output driving transistor geometries.

A method for the delivery of power to subthreshold (sub-Vt) circuits uses unused current during idle-mode operation of super-threshold (super-Vt) circuits is used to supply sub-Vt circuits. Algorithmic and circuit techniques use dynamic management of idle cores when reusing the leakage current of the idle cores. A scheduling algorithm, longest idle time-leakage reuse (LIT-LR) enables energy efficient reuse of leakage current, which generates a supply voltage of 340 mV with less than ±3% variation across the tt, ff, and ss process corners. The LIT-LR algorithm reduces the energy consumption of the switch and the peak power consumption by, respectively, 25% and 7.4% as compared to random assignment of idle cores for leakage reuse. Second, a usage ranking based algorithm, longest idle time-simultaneous leakage reuse and power gating (LIT-LRPG) enables simultaneous implementation of power gating (PG) and leakage reuse in a multiprocessor system-on-chip (MPSoC) platform.

According to an aspect, a current mode logic circuit comprise a first transistor to which an input voltage is applied, a second transistor connected in parallel with the first transistor; and a voltage sampling circuit which is connected to the first transistor and the second transistor and resets an output voltage output by integrating the input voltage for a predetermined set time (T) in a manner in which the output voltage is integrated in a direction opposite to a direction in which the input voltage is integrated for the predetermined set time (T).

A size setting method for a power switch transistor and a system thereof are proposed. A load current extracting step is performed to extract a first load current and a second load current. A limited voltage drop calculating step is performed to calculate a limited voltage drop according to a speed proportional value, the first load current and the second load current. A standard supply current calculating step is performed to calculate a standard supply current according to the limited voltage drop. A simulated supply current calculating step is performed to calculate a simulated supply current according to the standard supply current, the limited voltage drop and a line voltage value. A size setting step is performed to compare the first load current with the simulated supply current to calculate a size parameter, and set a size of the power switch transistor according to the size parameter.

There are provided an apparatus and method for performing impedance control (ZQ) calibration without a ZQ pin and an external resistor. The apparatus includes an output driver circuit connected to a signal pin interfacing with an external device; a register control word (RCW) configured to store an output driver impedance parameter related to a pull-up output voltage (VOH) condition of the signal pin; and a ZQ calibration circuit connected to the signal pin and configured to perform calibration using a VOH target level of the signal pin and control a termination resistance of the signal pin.

An integrated circuit with self-reference impedance includes an input/output pin provided for connection to an external impedance, a local impedance, a reference power circuit, a switching circuit, and a control circuit. The switching circuit is configured to conduct a connection between the input/output pin and the reference power circuit in a first state and to conduct a connection between the local impedance and the reference power circuit in a second state. The control circuit is configured to detect whether the external impedance is connected to the input/output pin or not and to generate a detection signal. The control circuit controls the switching circuit into the first state or the second state according to the detection signal. In the first state, the reference power circuit generates a reference signal according to the external impedance. In the second state, the reference power circuit generates the reference signal according to the local impedance.

An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry. The CMOS circuitry includes a p-channel transistor network that includes at least one p-channel transistor having a gate-induced drain leakage (GIDL) current. The IC further includes a native metal oxide semiconductor (MOS) transistor coupled to supply a bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor.

The present invention provides an output buffer including a first transistor, a second transistor and a pad-tracking circuit is disclosed. The first transistor is coupled between a supply voltage and an output node, wherein the output node is coupled to a pad. The second transistor is coupled between the output node and a reference voltage. The pad-tracking circuit is coupled to the control circuit and the first transistor, and is configured to generate a gate control signal to a gate electrode of the first transistor. The output buffer is selectively operated in an input mode and a fail-safe mode, and when the output buffer switches between the input mode and the fail-safe mode and the supply voltage of the first transistor ramps up or ramps down, the pad-tracking circuit generates the gate control signal to the gate electrode of the first transistor according to the voltage of the pad.

The present invention provides a processor including a core circuit, a plurality of clock signal generation circuits, a multiplexer and a detection circuit is disclosed. The core circuit is supplied by a supply voltage. The plurality of clock signal generation circuits are configured to generate a plurality of clock signals with different frequencies, respectively, wherein a number of the plurality of clock signals is equal to or greater than three. The multiplexer is configured to receive the plurality of clock signals, and to select one of the plurality of clock signals to serve as an output clock signal according to a control signal, wherein the core circuit uses the output clock signal to serve as an operating clock. The detection circuit is configured to detect a level of the supply voltage received by the core circuit in a real-time manner, to generate the control signal.