A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.

A flip-flop includes an input switching circuit configured to output an intermediate signal based on an input signal and at least one of a phase of a clock signal or a phase of an inverted clock signal, the phase of the inverted clock signal being opposite to the phase of the clock signal, and block application of a driving voltage to at least one circuit element of the input switching circuit in response to receiving a reset signal representing a reset operation of the flip-flop, and a latch circuit configured to generate an output signal based on the intermediate signal according to the at least one of the phase of the clock signal or the phase of the inverted clock signal.

An integrated circuit assembly may include an integrated circuit having a plurality of programmable logic sectors and an interposer circuit positioned adjacent to the integrated circuit. The interposer circuit may include at least one voltage regulator that distributes a voltage to at least one of the plurality of programmable logic sectors and at least one thermal sensor that measures a temperature of the at least one of the plurality of programmable logic sectors.

A repeater for open-drain bus communication and a system including the same is provided. The repeater includes at least one repeating unit having an A-side terminal connected to an A-side open-drain bus, and a B-side terminal electrically connected to a B-side open-drain bus. The repeater has a first mode to receive a signal at the A-side and to produce a signal at the B-side. The repeating unit includes a B-side accelerator element connected to the B-side terminal. The repeating unit when in a first mode includes a first control unit to, control the B-side accelerator element to pull up a voltage at the B-side when the voltage at the A-side surpasses a first threshold voltage during a rising edge of the voltage, and to subsequently control the B-side accelerator element to stop pulling up the voltage at the B-side when the voltage at the B-side surpasses a second threshold voltage.

An aspect relates to an apparatus including a first and second power rails; a first set of power switch cells coupled to the first and second power rails, the first set of power switch cells being cascaded from an output to an input of a control circuit; and a second set of power switch cells coupled to the first and second power rails, the second set of power switch cells being coupled to one of a pair of cells of the first set, the first output, and the first input of the control circuit. Another aspect relates to a method including propagating a control signal via a first set of cascaded power switch cells to sequentially couple a first power rail to a second power rail; and propagating the control signal via a second set of power switch cells coupled between a pair of cells of the first set.

An integrated circuit according to one or more embodiments may include a terminal to which an impedance element and a power supply having a predetermined potential can be connected. The integrated circuit may be configured to change a potential of one of electrodes of the impedance element connected to the terminal, detect a change in electrical characteristics of the terminal based on characteristics of the impedance element when the potential of the one electrode of the impedance element is changed, to determine a setting condition among a plurality of setting conditions that are used for an operation of the integrated circuit, store the setting condition in a storage, and use the setting condition stored in the storage for the operation of the integrated circuit.

A serializer clock delay optimization system comprising a multiplexer configured to receive two or more low-rate data signals and a multiplexer control signal. The multiplexer generates a full-rate data signal by combining the two or more low-rate data signals such that the multiplexer control signal determines sampling time of the low-rate data signals. A data monitor monitors and evaluates the full-rate data signal to generate a quality value representing the quality of the full-rate data signal. The quality of the full-rate data signal is based on the accuracy of the sampling time of the low-rate data signals. A delay controller processes the quality value to generate a delay control signal or value. A delay receives a clock signal and the delay control signal or value. Responsive to the delay control signal or value, the delay modifies the timing of the clock signal to create the multiplexer control signal.

A power gating circuit includes inverters and a voltage divider sub-circuit, a latch comparator, and a gated switch sub-circuit connected to an external power supply circuit of 5V, respectively. The voltage divider sub-circuit is configured to divide a voltage of 5V and output a first voltage and a second voltage to the latch comparator and the gated switch sub-circuit, both voltage values of the first voltage and the second voltage are smaller than a withstand voltage value of a field effect transistor, and the voltage value of the first voltage is greater than that of the second voltage; the latch comparator is configured to compare two signals output by the inverters and latch a comparison result; and the gated switch sub-circuit is further connected with the latch comparator to control an output voltage, thereby improving the stability of the circuit, and extending the using life of the entire circuit.

The present disclosure provides an SST driving circuit, a chip, and a driving output method. The SST driving circuit includes: a signal driver for driving and outputting a signal to be driven, the signal driver including termination resistors; a first electrostatic current discharge module, providing first discharge paths for electrostatic currents generated in the signal driver; a second electrostatic current discharge module, connected in series with the termination resistors, providing second discharge paths for the electrostatic currents; and a power clamp, used for conducting the power clamp circuit, the first discharge paths and the second discharge paths when a power supply voltage of the signal driver exceeds a clamping voltage. The present disclosure provides different discharge paths, which effectively reduces voltage borne by a protected device through a voltage division method, and improves the device's ability to protect against electrostatic discharge.

An off chip driver circuit includes a pull-up circuit and a pull-down circuit. The pull-up circuit includes several first transistors and a first resistance circuit coupled between the first transistors and a input/output pad. The first transistors generate a first voltage to the first resistance circuit. The first resistance circuit transmits, in response to a first control signal, the first voltage to the input/output pad and to have a variable resistance according to the first control signal. The pull-down circuit includes several second transistors and a second resistance circuit coupled between the second transistors and the input/output pad. The second transistors generate a second voltage to the second resistance circuit. The second resistance circuit transmits, in response to a second control signal, the second voltage to the input/output pad and to have a variable resistance according to the second control signal.