A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.

An electronic device includes a driving control signal generation circuit configured to generate first and second driving control signals and a driving switching control signal. The electronic device also includes a switching control signal driving circuit configured to drive a switching control signal to a first voltage on the basis of the first driving control signal and the driving switching control signal or drive the switching control signal to a second voltage on the basis of the second driving control signal, depending on whether a power-down mode is performed.

A voltage level-shifting circuit for an integrated circuit includes an input terminal receiving a voltage signal referenced to an input/output (PO) voltage level. A transistor overvoltage protection circuit includes a first p-type metal oxide semiconductor (PMOS) transistor includes a source coupled to the second voltage supply, a gate receiving an enable signal, and a drain connected to a central node. A first n-type metal oxide semiconductor (NMOS) transistor includes a drain connected to the central node, a gate connected to the input terminal, and a source connected to an output terminal. A second NMOS transistor includes a drain connected to the input terminal, a gate connected to the central node, and a source connected to the output terminal.

Some embodiments provide a voltage-level shifter circuit comprising a cross-coupled transistor pull-up network that includes a plurality of diode-connected transistors configured to cause the state of the cross-coupled transistor network to switch at a low current through a pull-down network coupled thereto, such as a current corresponding to near-threshold voltage or sub-threshold voltage operation of the pull-down network.

A semiconductor device that can automatically transition from a standby mode to a deep power down (DPD) mode is provided. The semiconductor device includes a DPD controller supporting the DPD mode and multiple internal circuits. The DPD controller measures a time since a time point of entering the standby mode and generates multiple power down enable signals for further reducing power consumption in the standby mode in response to elapse of a measurement time, so that operations of the multiple internal circuits are stopped in stages.

An arbiter for use with a plurality of request signals is presented. The arbiter includes a sequence identifier to identify an order between the plurality of request signals. The arbiter provides a plurality of output signals in which each output signal is associated with a request signal. When the request signals are provided in a sequential order the output signals are provided in the identified sequential order. When the request signals are provided substantially at the same time the output signals are provided in an arbitrary sequential order. A corresponding signal arbitration method and an electronic circuit comprising the arbiter are also presented.

A semiconductor device having a cell region, the cell region including a first set of one or more first blocks and a second set of one or more second blocks. Each of the first blocks including a clock gate and each of the second blocks includes a decoupling capacitor. The first set has two or more first blocks and/or the second set has two or more second blocks. The first blocks of the first set are interleaved with the second blocks of the second set.

A circuit includes a P-channel transistor formed in a P-well and an N-channel transistor formed in an N-well. The first P-channel transistor has a control electrode connected to the P-well. The N-channel transistor is coupled in series with the P-channel transistor and has a control electrode connected to the N-well. Connecting the control electrodes of the P-channel and N-channel transistors to respective P-well and N-well effectively reduces crowbar current in the circuit.

A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The sequential circuit includes a 3-input majority gate having first, second, and third inputs, and a first output. The sequential circuit includes a driver coupled to the first output, wherein the driver is to generate a second output. The sequential circuit further includes an exclusive-OR (XOR) gate to receive a clock and the second output, wherein the XOR gate is to generate a third output which couples to the second input, where the first input is to receive a data, and wherein the third input is to receive the second output.

A circuit and method are provided to monitor a clock for a data processor. The method includes receiving a clock signal and producing a first voltage proportional to a frequency of the clock signal. The first voltage is converted to a digital signal. During an initialization mode, the method ensures the clock signal is at a desired frequency and scales the digital signal using a first configurable ratio to produce a high threshold value. When changing from the initialization mode to an operating mode, the method ceases to scale the digital signal and maintains the high threshold value. During the operating mode, the method compares the digital signal to the high threshold value to determine if the clock signal has been increased in frequency beyond a desired level, and if so, triggers an overclock alert to a system management circuit of the data processor.