An integrated circuit comprising: a substrate; a configurable tank circuit on the substrate, the configurable tank circuit including: a first pair of inductive loops driven in parallel in each of a first configuration and a second configuration, each of the inductive loops in the first pair enclosing a corresponding capacitive element connected in parallel with that inductive loop; a second pair of inductive loops driven in parallel with the first pair of loops in the second configuration, the second pair of inductive loops undriven in the first configuration; and a switch arrangement that alternately places the configurable tank circuit into either of the first and second configurations; and an oscillation driver that drives the configurable tank circuit at a tunable resonance frequency.

The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

A tracking apparatus for a machine having an operation assembly is disclosed. The tracking apparatus has an electric relay configured to be connected to the operation assembly, a tracking device that is connected to the electric relay, and an electronic payment device that is connected to the electric relay. The electric relay is configured to transfer a first electrical pulse from the operation assembly to the tracking device. The electric relay is configured to transfer a second electrical pulse from either the electronic payment device or the operation assembly to the tracking device. The relay transfers the first electrical pulse or the second electrical pulse when the operation assembly performs an operation.

A tracking apparatus for a machine having an operation assembly is disclosed. The tracking apparatus has an electric relay configured to be connected to the operation assembly, a tracking device that is connected to the electric relay, and an electronic payment device that is connected to the electric relay. The electric relay is configured to transfer a first electrical pulse from the operation assembly to the tracking device. The electric relay is configured to transfer a second electrical pulse from either the electronic payment device or the operation assembly to the tracking device. The relay transfers the first electrical pulse or the second electrical pulse when the operation assembly performs an operation.

A pulse generation circuit has: an edge detector detecting a pulse edge in an input signal to generate edge detection signals; a clock generator generating a clock signal according to the edge detection signals; a frequency divider dividing the frequency of the clock signal to generate a frequency-divided clock signal; an input pad for receiving a test mode switch signal from a tester; and an output pad for outputting the frequency-divided clock signal to the tester. The edge detector can generate the edge detection signals by detecting a pulse edge not in the input signal but in the clock signal or in the inverted clock signal obtained by inverting the logic level of the clock signal when the test mode switch signal is being fed in. The signal delay time in the edge detector is adjustable according to the period of the frequency-divided clock signal as measured by the tester.

A pulse generation circuit has: an edge detector detecting a pulse edge in an input signal to generate edge detection signals; a clock generator generating a clock signal according to the edge detection signals; a frequency divider dividing the frequency of the clock signal to generate a frequency-divided clock signal; an input pad for receiving a test mode switch signal from a tester; and an output pad for outputting the frequency-divided clock signal to the tester. The edge detector can generate the edge detection signals by detecting a pulse edge not in the input signal but in the clock signal or in the inverted clock signal obtained by inverting the logic level of the clock signal when the test mode switch signal is being fed in. The signal delay time in the edge detector is adjustable according to the period of the frequency-divided clock signal as measured by the tester.

A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

A device for generating an output signal, formed as a pulse sequence, with a sensor and a controller. The sensor generates a sensor signal based on a measurand determined by the sensor. The controller determines a number of pulses of a timing signal that are generated chronologically between two pulse edges of the sensor signal, the timing signal being generated by a timing signal generator. The controller also generates an intermediate timing signal formed as a pulse sequence, where the period duration of the intermediate timing signal is equal to the period duration of the timing signal multiplied with a factor that is equal to the determined number of pulses of the timing signal, divided by a predetermined divisor. The controller generates the output signal based on the intermediate timing signal.

A device for generating an output signal, formed as a pulse sequence, with a sensor and a controller. The sensor generates a sensor signal based on a measurand determined by the sensor. The controller determines a number of pulses of a timing signal that are generated chronologically between two pulse edges of the sensor signal, the timing signal being generated by a timing signal generator. The controller also generates an intermediate timing signal formed as a pulse sequence, where the period duration of the intermediate timing signal is equal to the period duration of the timing signal multiplied with a factor that is equal to the determined number of pulses of the timing signal, divided by a predetermined divisor. The controller generates the output signal based on the intermediate timing signal.