A semiconductor device includes a mode determination unit configured to determine a power mode based on a temperature of the semiconductor device and a reference temperature, the power mode including one of a first mode which sets the operating frequency of the operation clock to be a first operating frequency and a second mode which sets the operating frequency of the operation clock to be a second operating frequency, and output a control signal according to the power mode to a clock generating unit.

In accordance with an embodiment, a circuit includes an input clock terminal, an output clock terminal, a first input data terminal, and a set of input data terminals having a number of terminals. A divide-by-two block is coupled to the output clock terminal. A modular one-shot clock divider is coupled between the input clock terminal and the divide-by-two block. The modular one-shot clock divider is further coupled to the set of input data terminals. An intermediate clock generation block is coupled between the input clock terminal and the modular one-shot clock divider. The intermediate clock generation block includes a first digital logic block coupled between the input clock terminal and the modular one-shot clock divider. The first digital logic block is further coupled to the first input data terminal, and a clock-blocking block is coupled between the divide-by-two block and the first digital logic block.

In accordance with an embodiment, a circuit includes an input clock terminal, an output clock terminal, a first input data terminal, and a set of input data terminals having a number of terminals. A divide-by-two block is coupled to the output clock terminal. A modular one-shot clock divider is coupled between the input clock terminal and the divide-by-two block. The modular one-shot clock divider is further coupled to the set of input data terminals. An intermediate clock generation block is coupled between the input clock terminal and the modular one-shot clock divider. The intermediate clock generation block includes a first digital logic block coupled between the input clock terminal and the modular one-shot clock divider. The first digital logic block is further coupled to the first input data terminal, and a clock-blocking block is coupled between the divide-by-two block and the first digital logic block.

A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

A circuit receives an input clock pulse signal characterized by a first frequency and a first pulse width, and produces an output pulse signal characterized by a second frequency that is half of the first frequency and a second pulse width that is equal to the first pulse width. The circuit also includes a first D-flipflop, a first inverter, a first Schmitt trigger, and a first AND gate. The first D-flipflop includes a clock input terminal for receiving the input clock pulse signal and an output terminal for producing a first data output. The first inverter couples the output terminal and a data input terminal of the first D-flipflop. A first Schmitt trigger receives the input clock pulse signal and provides a first delayed input clock signal. The first AND gate receives the first data output and the first delayed input clock signal, and provides the output pulse signal.

A clock signal frequency divider according to one aspect of the present disclosure includes: an output signal generation circuit configured to generate, from pulses of a received input clock signal, an output clock signal including a repetition of a periodic pattern signal in which a pulse of a mask pulse number is masked among consecutive pulses of a periodic pulse number, the periodic pattern signal including a marker portion including at least one unmasked pulse at a start portion of the periodic pattern signal; and an output circuit configured to output the output clock signal, wherein the output signal generation circuit generates the periodic pattern signal in such a way that a pattern of a timing of the at least one unmasked pulse of the marker portion does not appear in a portion other than a portion corresponding to the marker portion in the output clock signal.

A clock signal frequency divider according to one aspect of the present disclosure includes: an output signal generation circuit configured to generate, from pulses of a received input clock signal, an output clock signal including a repetition of a periodic pattern signal in which a pulse of a mask pulse number is masked among consecutive pulses of a periodic pulse number, the periodic pattern signal including a marker portion including at least one unmasked pulse at a start portion of the periodic pattern signal; and an output circuit configured to output the output clock signal, wherein the output signal generation circuit generates the periodic pattern signal in such a way that a pattern of a timing of the at least one unmasked pulse of the marker portion does not appear in a portion other than a portion corresponding to the marker portion in the output clock signal.

A circuit receives an input clock pulse signal characterized by a first frequency and a first pulse width, and produces an output pulse signal characterized by a second frequency that is half of the first frequency and a second pulse width that is equal to the first pulse width. The circuit also includes a first D-flipflop, a first inverter, a first Schmitt trigger, and a first AND gate. The first D-flipflop includes a clock input terminal for receiving the input clock pulse signal and an output terminal for producing a first data output. The first inverter couples the output terminal and a data input terminal of the first D-flipflop. A first Schmitt trigger receives the input clock pulse signal and provides a first delayed input clock signal. The first AND gate receives the first data output and the first delayed input clock signal, and provides the output pulse signal.

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.