A method of sensing a temperature of a semiconductor device, includes: measuring, by a time measuring circuit, time until a count value, which is obtained from a counter by counting a first signal having a frequency corresponding to a first voltage, reaches a largest count value which can be counted by the counter; and obtaining, by the counter, a piece of digital information corresponding to the first voltage based on a count value obtained by counting a second signal having a frequency corresponding to a second voltage, which is different from the first voltage, based on the time measured by the time measuring circuit, the first voltage depending upon the temperature of the semiconductor device.

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

The present disclosure provides a frequency generator, and belongs to the technical field of communications. The frequency generator provided by the present disclosure includes: N stages of mixing modules and N stages of comb spectrum generation modules. Each of the comb spectrum generation modules is configured to provide a mixing module in a same stage as the comb spectrum generation modules with one stage of fundamental signal group generated according to a second reference signal; and different stages of fundamental signal groups are generated based on different second reference signals. A 1.sup.st-stage mixing module generates a 1.sup.st-stage mixed signal according to a 1.sup.st-stage fundamental signal group and a first reference signal, and the 1.sup.st-stage fundamental signal group includes a plurality of harmonic signals with a first frequency as a fundamental frequency.

The present disclosure provides a frequency generator, and belongs to the technical field of communications. The frequency generator provided by the present disclosure includes: N stages of mixing modules and N stages of comb spectrum generation modules. Each of the comb spectrum generation modules is configured to provide a mixing module in a same stage as the comb spectrum generation modules with one stage of fundamental signal group generated according to a second reference signal; and different stages of fundamental signal groups are generated based on different second reference signals. A 1.sup.st-stage mixing module generates a 1.sup.st-stage mixed signal according to a 1.sup.st-stage fundamental signal group and a first reference signal, and the 1.sup.st-stage fundamental signal group includes a plurality of harmonic signals with a first frequency as a fundamental frequency.

Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors.

A frequency synthesizer comprising a reference oscillator configured to generate a first clock signal with a reference frequency and a divider controller configured to receive the first clock signal, a second clock signal, and a multiplier value. The divider controller is configured to obtain a ratio of a frequency of the first clock signal to a frequency of the second clock signal and divide the resulting ratio by the multiplier value to obtain controller output value. A divider is configured to receive the first clock signal and controller output value and output an output clock signal with a frequency equal to the frequency of the first clock signal divided by the controller output value.

In accordance with an embodiment, a circuit includes an input clock terminal, an output clock terminal, a first input data terminal, and a set of input data terminals having a number of terminals. A divide-by-two block is coupled to the output clock terminal. A modular one-shot clock divider is coupled between the input clock terminal and the divide-by-two block. The modular one-shot clock divider is further coupled to the set of input data terminals. An intermediate clock generation block is coupled between the input clock terminal and the modular one-shot clock divider. The intermediate clock generation block includes a first digital logic block coupled between the input clock terminal and the modular one-shot clock divider. The first digital logic block is further coupled to the first input data terminal, and a clock-blocking block is coupled between the divide-by-two block and the first digital logic block.

Design techniques for multi-modulus prescaler circuits that minimize the input-to-output delay dependence on the modulus control state or history. The feed-forward signal path inside a multi-modulus prescaler is identified, as well as all feedback paths connected to the feed-forward signal path. In various embodiments, one or more of several techniques may be applied to reduce capacitive load variations and signal coupling due to the modulus control state or history. For at least one component coupled to the feed-forward signal path and having a feedback path, a buffered feedback path may be created separate but parallel to a buffered feed-forward signal path. Double buffers may be added to some feedback paths directly coupled to the feed-forward path so that the forward signal path is not affected by load variations in such feedback paths.

Design techniques for multi-modulus prescaler circuits that minimize the input-to-output delay dependence on the modulus control state or history. The feed-forward signal path inside a multi-modulus prescaler is identified, as well as all feedback paths connected to the feed-forward signal path. In various embodiments, one or more of several techniques may be applied to reduce capacitive load variations and signal coupling due to the modulus control state or history. For at least one component coupled to the feed-forward signal path and having a feedback path, a buffered feedback path may be created separate but parallel to a buffered feed-forward signal path. Double buffers may be added to some feedback paths directly coupled to the feed-forward path so that the forward signal path is not affected by load variations in such feedback paths.