Systems and methods disclosed herein provide for a fractional feedback divider with reduced jitter at the output without increasing the input clock frequency and with minimal power increase. Embodiments of the system provide for interpolating, with a multiplexer, different output clock signals depending on whether an extra half period of resolution from the input clock is needed for a certain output clock cycle.

A circuit includes a counter circuit, a logic circuit, and a clock divider. The counter circuit includes a clock divider counter to be loaded with most significant bits of a divider value, and decremented at a same edge of each pulse of a clock signal. The logic circuit compares a value contained in the divider counter to a reference value and generates an end count signal as a function of the value contained in the divider counter matching the reference value, and transitions a toggle signal at a same edge of each pulse of the end count signal. The clock divider counter is reloaded with the most significant bits of the divider value as a function of the end count signal. The clock divider generates a divided version of the clock signal as a function of the toggle signal.

The present disclosure describes current steering phase control for current-mode logic (CML) circuits. In some aspects, a circuit for frequency division comprises a current sink connected to a ground rail. The circuit also includes first and second current-carrying branches of frequency-dividing circuitry operably connected to respective load resistors, which are connected to a power rail. A first switch element of the circuit is connected between the current sink and the first current-carrying branch and a second switch element of the circuit is connected between the current sink and the second current-carrying branch. The first and second switch elements may steer current sank by the current sink between the first and second current-carrying branches effective to alter a phase of a signal provided by the frequency division circuit.

Systems and methods for dividing input clock signals by programmable divide ratios can produce output clock signals with the delay from the input clock signal to the output clock signal independent of the value of the divide ratio and with the duty cycle of the output clock signal being 50% independent of the value of the divide ratio. An example programmable clock divider includes a modulo N counter that produces a count signal that counts modulo the divide ratio and a half-rate clock signal generator that produces a common half-rate clock signal, an even half-rate clock signal, and an odd half-rate clock signal that toggle at one-half the rate of the output clock signal. The common half-rate clock signal, the even half-rate clock signal, and the odd half-rate clock signal are combined to produce the output clock signal.

Systems and methods for dividing input clock signals by programmable divide ratios can produce output clock signals with the delay from the input clock signal to the output clock signal independent of the value of the divide ratio and with the duty cycle of the output clock signal being 50% independent of the value of the divide ratio. An example programmable clock divider includes a modulo N counter that produces a count signal that counts modulo the divide ratio and a half-rate clock signal generator that produces a common half-rate clock signal, an even half-rate clock signal, and an odd half-rate clock signal that toggle at one-half the rate of the output clock signal. The common half-rate clock signal, the even half-rate clock signal, and the odd half-rate clock signal are combined to produce the output clock signal.

A pleat counter and methods are provided to accurately count the number of pleats in a corrugated sheet of material to be used for the production of air filters. The pleat counter comprises a pleat detector mounted underneath a mounting board for counting the pleats. The mounting board is configured to position the pleat detector adjacent to the corrugated sheet of filter material. The pleat detector includes one or more sensors configured to detect the presence of individual pleats comprising the corrugated sheet. The pleat counter includes an interface configured to enable coupling the pleat counter with a data processing system. The data processing system may comprise any of a desktop, a tablet, a server, a mobile phone, a media player, a personal digital assistant (PDA), a personal communicator, a network router or hub, a wireless access point (AP) or repeater, a set-top box, or a combination thereof.

A pleat counter and methods are provided to accurately count the number of pleats in a corrugated sheet of material to be used for the production of air filters. The pleat counter comprises a pleat detector mounted underneath a mounting board for counting the pleats. The mounting board is configured to position the pleat detector adjacent to the corrugated sheet of filter material. The pleat detector includes one or more sensors configured to detect the presence of individual pleats comprising the corrugated sheet. The pleat counter includes an interface configured to enable coupling the pleat counter with a data processing system. The data processing system may comprise any of a desktop, a tablet, a server, a mobile phone, a media player, a personal digital assistant (PDA), a personal communicator, a network router or hub, a wireless access point (AP) or repeater, a set-top box, or a combination thereof.

Disclosed examples include frequency divider circuits to divide a high frequency first clock signal to generate an output clock signal at a lower frequency, including a delay circuit to provide a delayed clock signal, a divider circuit to provide a divided clock signal, a sub-sampling circuit to sub-sample the first clock signal with the divided clock signal, and a feedback circuit to set the delay value of the adjustable delay circuit according to the sub-sampled output signal.

Disclosed is an earphone, comprising a left receiver, a right receiver and a sound source input end. A main left loudspeaker and a secondary left loudspeaker are arranged in the left receiver, and a main right loudspeaker and a secondary right loudspeaker are arranged in the right receiver. The sound source input end includes a left channel audio input end and a right channel audio input end. The left channel audio input end is electrically connected to the secondary right loudspeaker via a third frequency divider, and the right channel audio input end is electrically connected to the secondary left loudspeaker via a fourth frequency divider. The third frequency divider is configured for performing frequency division processing on audio signals input by the left channel audio input end and transmitting the same to the secondary right loudspeaker, and the fourth frequency divider is configured for performing frequency division processing on the audio signals input by the right channel audio input end and transmitting the same to the secondary left loudspeaker. With the proposed earphone, users may be able to have unprecedented, real and natural environmental listening performance.

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.