A counter is provided. A charge distributing circuit includes a first switch, a second switch, a third switch, a fourth switch, a third capacitor and a fourth capacitor. A first terminal of the first switch and a first terminal of the third switch are connected to a first input terminal of an operational amplifier. A second terminal of the first switch is connected to a first terminal of the third capacitor and a first terminal of the fourth switch. A second terminal of the third switch is connected to a first terminal of the fourth capacitor and a first terminal of the second switch. A second terminal of the third capacitor and a second terminal of the fourth capacitor are grounded. A second terminal of the second switch and a second terminal of the fourth switch are coupled to a reference voltage.

A sensor interface circuit includes: an RF switch having a control node; a bias circuit electrically connected to the control node and applying, to the control node, a voltage at a first level or a second level corresponding to a linear region of a reflection characteristic; a first variable oscillation circuit electrically connectable to a first sensor; a second variable oscillation circuit electrically connectable to a second sensor; and a difference circuit electrically connected between the first variable oscillation circuit and the bias circuit, and between the second variable oscillation circuit and the bias circuit.

The present invention provides a semiconductor device having a sensor capable of improving precision while suppressing increase in occupation area. A semiconductor device has: a first counter; and a second counter (time measuring circuit) measuring time until a count value, which is obtained by counting a first signal having a frequency corresponding to a first voltage, reaches a largest count value which can be counted by the first counter. The first counter obtains a piece of digital information corresponding to the first voltage on the basis of a count value obtained by counting a second signal having a frequency corresponding to a second voltage, which is different from the first voltage, on the basis of the time measured by the time measuring circuit.

The present invention provides a semiconductor device having a sensor capable of improving precision while suppressing increase in occupation area. A semiconductor device has: a first counter; and a second counter (time measuring circuit) measuring time until a count value, which is obtained by counting a first signal having a frequency corresponding to a first voltage, reaches a largest count value which can be counted by the first counter. The first counter obtains a piece of digital information corresponding to the first voltage on the basis of a count value obtained by counting a second signal having a frequency corresponding to a second voltage, which is different from the first voltage, on the basis of the time measured by the time measuring circuit.

A circuit for sensing local operating properties of an integrated circuit is disclosed. The circuit may include one or more sensor circuits configured to sense the local operating properties of the integrated circuit. The sensor circuits may receive a supply voltage with a magnitude in a limited range from a digital power supply that is different from the digital power supply that provides power to functional circuits in the integrated circuit. Level shifters may be coupled to the sensor circuits to shift output signals from the sensor circuits to levels that correspond to the digital power supply that provides power to functional circuits in the integrated circuit. Counters and a shift register may be coupled to the level shifters to receive the shifted output signals, the values of which may be used to determine the local operating properties of the integrated circuit as sensed by the sensor circuits.

A signal distribution system includes: a first signal divider arranged to generate a first output oscillating signal according to a first input oscillating signal; a second signal divider arranged to generate a second output oscillating signal according to the first input oscillating signal; a first transmitting channel coupled to the first signal divider and the second divider for transmitting the first input oscillating signal to the first signal divider and the second signal divider; and a second transmitting channel coupled to the first signal divider and the second divider for transmitting a second input oscillating signal to the first signal divider and the second signal divider; wherein the first input oscillating signal has a first frequency, the second input oscillating signal has a second frequency, and the second frequency is smaller than the first frequency.

A circuit for sensing local operating properties of an integrated circuit is disclosed. The circuit may include one or more sensor circuits configured to sense the local operating properties of the integrated circuit. The sensor circuits may receive a supply voltage with a magnitude in a limited range from a digital power supply that is different from the digital power supply that provides power to functional circuits in the integrated circuit. Level shifters may be coupled to the sensor circuits to shift output signals from the sensor circuits to levels that correspond to the digital power supply that provides power to functional circuits in the integrated circuit. Counters and a shift register may be coupled to the level shifters to receive the shifted output signals, the values of which may be used to determine the local operating properties of the integrated circuit as sensed by the sensor circuits.

An agile frequency synthesizer with dynamic phase and pulse-width control is disclosed. In one aspect, the frequency synthesizer includes a count circuit configured to modify a stored count value by an adjustment value. The frequency synthesizer also includes an output clock generator configured to generate an output clock signal having rising and falling edges that are based at least in part on the stored count value satisfying a count threshold. The count circuit is further configured to alter at least one of the period or phase of the output clock signal based at least in part on modifying an adjustment rate of the count circuit.

An agile frequency synthesizer with dynamic phase and pulse-width control is disclosed. In one aspect, the frequency synthesizer includes a count circuit configured to modify a stored count value by an adjustment value. The frequency synthesizer also includes an output clock generator configured to generate an output clock signal having rising and falling edges that are based at least in part on the stored count value satisfying a count threshold. The count circuit is further configured to alter at least one of the period or phase of the output clock signal based at least in part on modifying an adjustment rate of the count circuit.

An electronic circuit which is a high speed CMOS logic circuit to divide the frequency of an input signal is provided. The electronic circuit comprises a ring oscillator. The ring oscillator comprises a plurality of gated inverters. At least one of the gated inverters is configured to receive an oscillating signal and a control signal at two complementary inputs. The electronic circuit is configured to be partially gated such that a divide ratio is selectable. By means of clock partial gating, open loop clock buffering and avoiding slow combinatory logic in the data path, a very high speed multi-moduli clock divider is achieved.