Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

A back side illuminated image sensor may operate using the single-photon avalanche diode (SPAD) concept in a Geiger mode of operation for single photon detection. The image sensor may be implemented using two layer stacking with a silicon on insulator (SOI) chip. The chip-to-chip electrical connections between the top level image sensing chip and the second level ASIC circuit chip may be realized at each pixel with a single bump connection per pixel. A light level signal may be obtained from pixels that have photon counting capabilities while a distance measurement signal for 3-dimensional imaging may be obtained from pixels that have time-of-flight (ToF) detection capabilities. Both types of pixels may be integrated within the same array and use the same SPAD structure placed on the top chip.

A radar system includes: a processing device arranged to generate a plurality of phase shifting digital signals; a plurality of transmitting devices for generating an RF beam according to the plurality of phase shifting digital signals during a first mode; a plurality of first receiving devices for generating a plurality of first digital signals according to a plurality of first incoming signals, respectively, during a second mode; and a plurality of second receiving devices for generating a plurality of second digital signals according to a plurality of second incoming signals, respectively, during the second mode. The processing device is further arranged to distinguish a first object and a second object when the RF beam hits the first object and the second object, and the first object and the second object have a same radial speed and are located at a same range.

A signal divider includes: a dividing circuit arranged to generate an output oscillating signal according to a first input oscillating signal; and a signal generating circuit, coupled to the dividing circuit, for generating an injection signal to the dividing circuit. The dividing circuit is arranged to generate the output oscillating signal with a predetermined phase according to the injection signal and the first input oscillating signal.

An integrated circuit comprising: a substrate; a configurable tank circuit on the substrate, the configurable tank circuit including: a first pair of inductive loops driven in parallel in each of a first configuration and a second configuration, each of the inductive loops in the first pair enclosing a corresponding capacitive element connected in parallel with that inductive loop; a second pair of inductive loops driven in parallel with the first pair of loops in the second configuration, the second pair of inductive loops undriven in the first configuration; and a switch arrangement that alternately places the configurable tank circuit into either of the first and second configurations; and an oscillation driver that drives the configurable tank circuit at a tunable resonance frequency.

An integrated circuit comprising: a substrate; a configurable tank circuit on the substrate, the configurable tank circuit including: a first pair of inductive loops driven in parallel in each of a first configuration and a second configuration, each of the inductive loops in the first pair enclosing a corresponding capacitive element connected in parallel with that inductive loop; a second pair of inductive loops driven in parallel with the first pair of loops in the second configuration, the second pair of inductive loops undriven in the first configuration; and a switch arrangement that alternately places the configurable tank circuit into either of the first and second configurations; and an oscillation driver that drives the configurable tank circuit at a tunable resonance frequency.

An LC oscillator has a tank driver connected to cause a matched-resistance LC tank to oscillate. The LC tank has an inductor leg in parallel with a capacitor leg. The inductor leg has an explicit inductor having an implicit resistance level R.sub.L. The capacitor leg has an explicit capacitor having an implicit resistance level R.sub.C connected in series with an explicit resistor having an explicit resistance level R.sub.R, where R.sub.M=(R.sub.C+R.sub.R) is substantially equal to R.sub.L. The LC oscillator may have a non-trimmable LC tank and be part of a temperature-compensated frequency reference generator having standalone frequency adjustment circuitry that offers better than 0.1% frequency accuracy (after single trim and batch calibration) over process, voltage, and temperature variations, and lifetime, which can serve as a low-cost replacement for a crystal oscillator for many applications.

A tracking apparatus for a machine having an operation assembly is disclosed. The tracking apparatus has an electric relay configured to be connected to the operation assembly, a tracking device that is connected to the electric relay, and an electronic payment device that is connected to the electric relay. The electric relay is configured to transfer a first electrical pulse from the operation assembly to the tracking device. The electric relay is configured to transfer a second electrical pulse from either the electronic payment device or the operation assembly to the tracking device. The relay transfers the first electrical pulse or the second electrical pulse when the operation assembly performs an operation.

A tracking apparatus for a machine having an operation assembly is disclosed. The tracking apparatus has an electric relay configured to be connected to the operation assembly, a tracking device that is connected to the electric relay, and an electronic payment device that is connected to the electric relay. The electric relay is configured to transfer a first electrical pulse from the operation assembly to the tracking device. The electric relay is configured to transfer a second electrical pulse from either the electronic payment device or the operation assembly to the tracking device. The relay transfers the first electrical pulse or the second electrical pulse when the operation assembly performs an operation.

A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.