Systems and methods are provided for compensating for mechanical acceleration at a reference oscillator. A reference oscillator provides an oscillator output signal and an accelerometer on a same platform as the reference oscillator, such that mechanical acceleration at the reference oscillator is detected at the accelerometer to produce a measured acceleration. A filter assembly, having an associated set of filter weights, receives the measured acceleration from the accelerometer and provides a tuning control signal responsive to the measured acceleration to a frequency reference associated with the system. An adaptive weighting component receives the oscillator output signal of the reference oscillator and an external signal that is provided from a source external to the platform and adjusts the set of filter weights for the filter assembly based on a comparison of the external signal and the oscillator output signal.

Systems and methods are provided for compensating for mechanical acceleration at a reference oscillator. A reference oscillator provides an oscillator output signal and an accelerometer on a same platform as the reference oscillator, such that mechanical acceleration at the reference oscillator is detected at the accelerometer to produce a measured acceleration. A filter assembly, having an associated set of filter weights, receives the measured acceleration from the accelerometer and provides a tuning control signal responsive to the measured acceleration to a frequency reference associated with the system. An adaptive weighting component receives the oscillator output signal of the reference oscillator and an external signal that is provided from a source external to the platform and adjusts the set of filter weights for the filter assembly based on a comparison of the external signal and the oscillator output signal.

Techniques are disclosed relating to detecting supply voltage events and performing corrective actions. In some embodiments, an apparatus includes sensor circuitry and control circuitry. In some embodiments, the sensor circuitry is configured to monitor supply voltage from a power supply and detect a load release event that includes an increase in the supply voltage that meets one or more pre-determined threshold parameters. In some embodiments, the control circuitry is configured to increase clock cycle time for operations performed by circuitry powered by the supply voltage during a time interval, wherein the time interval corresponds to ringing of the supply voltage that reduces the supply voltage and results from the load release event. In some embodiments, the disclosed techniques may reduce transients in supply voltage (which may avoid equipment damage and computing errors) and may allow for reduced voltage margins (which may reduce overall power consumption).

Techniques are disclosed relating to detecting supply voltage events and performing corrective actions. In some embodiments, an apparatus includes sensor circuitry and control circuitry. In some embodiments, the sensor circuitry is configured to monitor supply voltage from a power supply and detect a load release event that includes an increase in the supply voltage that meets one or more pre-determined threshold parameters. In some embodiments, the control circuitry is configured to increase clock cycle time for operations performed by circuitry powered by the supply voltage during a time interval, wherein the time interval corresponds to ringing of the supply voltage that reduces the supply voltage and results from the load release event. In some embodiments, the disclosed techniques may reduce transients in supply voltage (which may avoid equipment damage and computing errors) and may allow for reduced voltage margins (which may reduce overall power consumption).

Disclosed is a voltage-controlled oscillator (VCO) capable of providing an effective high VCO gain against slow change of an input voltage caused by the variation of manufacturing processes, temperature, voltage, etc. and providing an effective low VCO gain against rapid change of the input voltage for reducing jitter. The VCO includes: an input circuit generating an input current according to an input voltage; a first current supply circuit generating a first output current according to the input current; a second current supply circuit generating a second output current according to the input current; a filter coupled to the input circuit and the second current supply circuit and configured to slow down the influence caused by the variation of the input current on the second current supply circuit; and an oscillating circuit generating an output clock according to the first output current and the second output current.

A time synchronization device adapted for an electronic apparatus, an electronic apparatus, a time synchronization system and a time synchronization method. The time synchronization device includes: a signal generating circuit and a time adjusting circuit. The signal generating circuit includes: a control circuit, configured to generate a frequency control word; and a signal adjusting circuit, configured to receive the frequency control word and an input signal having an initial frequency, and to generate and output an output signal having a target frequency based on the frequency control word and the input signal. The time adjusting circuit is configured to perform a synchronization adjusting operation on a clock signal of the electronic apparatus based on the output signal having the target frequency.

A tracking system for a digital Phase Locked Loop (PLL), the tracking system including a PLL model configured to emulate an actual internal PLL signal, wherein the emulation is based on another internal PLL signal received from the digital PLL and on an estimated analog PLL parameter of the PLL model; and a tracker configured to compare the emulated internal PLL signal with the actual internal PLL signal, and to update the estimated analog PLL parameter according to a minimization algorithm that minimizes a result of the comparison.

A tracking system for a digital Phase Locked Loop (PLL), the tracking system including a PLL model configured to emulate an actual internal PLL signal, wherein the emulation is based on another internal PLL signal received from the digital PLL and on an estimated analog PLL parameter of the PLL model; and a tracker configured to compare the emulated internal PLL signal with the actual internal PLL signal, and to update the estimated analog PLL parameter according to a minimization algorithm that minimizes a result of the comparison.

An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations. The digital circuitry regulates the digital input supply voltage to stabilize the resolution of the TDC across the PVT variations. This stabilization of the resolution of the TDC can cause the ADPLL to maintain a fixed in-band phase noise across the PVT variations.

An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations. The digital circuitry regulates the digital input supply voltage to stabilize the resolution of the TDC across the PVT variations. This stabilization of the resolution of the TDC can cause the ADPLL to maintain a fixed in-band phase noise across the PVT variations.