A cyclical pulsing oscillator having a pulse repetition rate close to a crystal resonant frequency in an oscillator provides more useful start-up energy to the crystal oscillator circuit and thus provides much faster start-up time. The start-up pulsing oscillator runs for a number of cycles or until the crystal oscillator amplitude as built up to a desired value. The pulsing oscillator may have a repetition rate of from about one-third to about one-half the crystal resonant frequency, thus providing more useful start-up energy to the crystal oscillator circuit.

A cyclical pulsing oscillator having a pulse repetition rate close to a crystal resonant frequency in an oscillator provides more useful start-up energy to the crystal oscillator circuit and thus provides much faster start-up time. The start-up pulsing oscillator runs for a number of cycles or until the crystal oscillator amplitude as built up to a desired value. The pulsing oscillator may have a repetition rate of from about one-third to about one-half the crystal resonant frequency, thus providing more useful start-up energy to the crystal oscillator circuit.

The disclosed apparatus may include (1) a first transistor whose (A) first terminal is electrically coupled to an enable node, (B) second terminal is electrically coupled to a feedback node, and (C) third terminal is electrically coupled to a ground node, (2) a second transistor whose (A) first terminal is electrically coupled to the feedback node, (B) second terminal is electrically coupled to the enable node, and (C) third terminal is electrically coupled to the ground node, (3) a resistor that is electrically coupled between the feedback node and the ground node, and (4) a diode that is electrically coupled between the feedback node and another resistor, wherein the other resistor is electrically coupled between the diode and an output-voltage node that provides electrical power to a computing device. Various other apparatuses, systems, and methods are also disclosed.

A circuit device includes a first oscillation circuit, a second oscillation circuit, a clock signal output circuit adapted to output a clock signal based on an output signal of the first oscillation circuit, and an output control circuit adapted to perform output control of the clock signal output circuit. The output control circuit includes a counter circuit adapted to perform a counting process based on an output signal of the second oscillation circuit, and the counter circuit outputs an output enable signal of the clock signal to the clock signal output circuit based on a result of the counting process.

A circuit device includes a first oscillation circuit, a second oscillation circuit, a clock signal output circuit adapted to output a clock signal based on an output signal of the first oscillation circuit, and an output control circuit adapted to perform output control of the clock signal output circuit. The output control circuit includes a counter circuit adapted to perform a counting process based on an output signal of the second oscillation circuit, and the counter circuit outputs an output enable signal of the clock signal to the clock signal output circuit based on a result of the counting process.

A circuit generates a number of oscillations. The circuit includes a first branch with at least one delay line introducing symmetrical delays on rising edges and on falling edges and at least one asymmetrical delay element introducing different delays on rising edges and on falling edges. The circuit further includes a second branch looped back on the first branch and including at least one delay line introducing symmetrical delays on rising edges and on falling edges.

A circuit generates a number of oscillations. The circuit includes a first branch with at least one delay line introducing symmetrical delays on rising edges and on falling edges and at least one asymmetrical delay element introducing different delays on rising edges and on falling edges. The circuit further includes a second branch looped back on the first branch and including at least one delay line introducing symmetrical delays on rising edges and on falling edges.

A crystal oscillator is started in a high power mode for a certain period of time to ensure starting oscillation with average grade crystals, then once the certain time period is over the oscillator switches into a low power mode and sustains oscillation with energy pulses triggered by and synchronized with the oscillator output frequency. These energy pulses may be generated on the positive, negative or both positive and negative edges of the clock output waveform.

A crystal oscillator is started in a high power mode for a certain period of time to ensure starting oscillation with average grade crystals, then once the certain time period is over the oscillator switches into a low power mode and sustains oscillation with energy pulses triggered by and synchronized with the oscillator output frequency. These energy pulses may be generated on the positive, negative or both positive and negative edges of the clock output waveform.

An oscillator using a supply regulation loop and a method of operating the oscillator are provided. The oscillator includes a reference voltage generator configured to generate reference voltages from a supply voltage, a supply regulation loop circuit including a first operational amplifier and a transistor, the first operational amplifier being configured to receive a first reference voltage of the reference voltages, and the transistor being connected to an output terminal of the first operational amplifier, and a frequency locked loop (FLL) circuit configured to generate a clock signal, based on an input voltage determined based on a current flowing in the transistor and a second reference voltage of the reference voltages, wherein the first operational amplifier may include an input terminal configured to receive the first reference voltage and to receive negative feedback from the transistor, and the output terminal being configured to generate an output voltage independent of noise of the supply voltage.