An oscillator circuit comprises a crystal oscillator arranged to generate an oscillation signal, a bias current generator arranged to supply a bias current to the crystal oscillator, and a feedback stage arranged to generate a feedback signal in response to an amplitude of the oscillation signal reaching an amplitude threshold. The bias current generator is arranged to: in response to a supply of power to the oscillator circuit being switched on, generate the bias current at an increasing level commencing from a first level; in response to the feedback signal, terminate the increasing; and during subsequent oscillation of the crystal oscillator, supply the bias current at a second level dependent on a final level of the bias current reached when the increasing is terminated.

An oscillator circuit comprises a crystal oscillator arranged to generate an oscillation signal, a bias current generator arranged to supply a bias current to the crystal oscillator, and a feedback stage arranged to generate a feedback signal in response to an amplitude of the oscillation signal reaching an amplitude threshold. The bias current generator is arranged to: in response to a supply of power to the oscillator circuit being switched on, generate the bias current at an increasing level commencing from a first level; in response to the feedback signal, terminate the increasing; and during subsequent oscillation of the crystal oscillator, supply the bias current at a second level dependent on a final level of the bias current reached when the increasing is terminated.

A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.

A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.

A calibration circuit for calibrating a peak detector configured to detect a signal peak amplitude of an oscillator, including: a calibration oscillator configured to be supplied by at least two different supply voltages to generate respective calibration signals; a calibration peak detector configured to detect a calibration signal peak amplitude of each of the calibration signals; and a logic circuit configured to calibrate the peak detector based on the detected calibration signal peak amplitudes.

A calibration circuit for calibrating a peak detector configured to detect a signal peak amplitude of an oscillator, including: a calibration oscillator configured to be supplied by at least two different supply voltages to generate respective calibration signals; a calibration peak detector configured to detect a calibration signal peak amplitude of each of the calibration signals; and a logic circuit configured to calibrate the peak detector based on the detected calibration signal peak amplitudes.

A voltage controlled oscillator (VCO) circuit generates an output signal having a frequency which is dependent on a control voltage. A current is generated which is itself dependent on an amplitude of the VCO circuit. The generated current accordingly tracks, to an extent, the temperature behavior of the oscillator within the VCO circuit. The oscillator is driven by the sum of the generated current and a control current dependent on the control voltage. The control voltage may, for example, be generated by a phase lock loop (PLL).

A semiconductor integrated circuit of embodiments includes a first MOS transistor configured to control conduction and non-conduction between a reference voltage point and a node, a second MOS transistor connected to the first MOS transistor via the node and configured to apply a voltage equal to or lower than a withstand voltage of the first MOS transistor to the node, a third MOS transistor configured to receive supply of a second voltage higher than the first voltage, and output an output signal of a signal level corresponding to a voltage range of the second voltage, and a switch circuit configured to make a voltage of the node a fixed voltage when the first MOS transistor is in an OFF state.

A 3-level ripple quantization scheme provides power transistor (MOS) strength-tuning mechanism focused on the transient clamp period. The 3-level ripple quantization scheme solves the digital low dropout's (D-LDO's) tradeoff between silicon area (e.g., decoupling capacitor size), quiescent power consumption (e.g., speed of comparators), wide load range, and optimal output ripple. The 3-level ripple quantization scheme eliminates oscillation risk from either wide dynamic range or parasitic by exploiting asynchronous pulse patterns. As such, ripple magnitude for both fast di/dt loading events and various steady-state scenarios are shrunk effectively, resulting significant efficiency benefits.

A 3-level ripple quantization scheme provides power transistor (MOS) strength-tuning mechanism focused on the transient clamp period. The 3-level ripple quantization scheme solves the digital low dropout's (D-LDO's) tradeoff between silicon area (e.g., decoupling capacitor size), quiescent power consumption (e.g., speed of comparators), wide load range, and optimal output ripple. The 3-level ripple quantization scheme eliminates oscillation risk from either wide dynamic range or parasitic by exploiting asynchronous pulse patterns. As such, ripple magnitude for both fast di/dt loading events and various steady-state scenarios are shrunk effectively, resulting significant efficiency benefits.