A method for achieving sub-pulsing during a state is described. The method includes receiving a clock signal from a clock source, the clock signal having two states and generating a pulsed signal from the clock signal. The pulsed signal has sub-states within one of the states. The sub-states alternate with respect to each other at a frequency greater than a frequency of the states. The method includes providing the pulsed signal to control power of a radio frequency (RF) signal that is generated by an RF generator. The power is controlled to be synchronous with the pulsed signal.

A method for achieving sub-pulsing during a state is described. The method includes receiving a clock signal from a clock source, the clock signal having two states and generating a pulsed signal from the clock signal. The pulsed signal has sub-states within one of the states. The sub-states alternate with respect to each other at a frequency greater than a frequency of the states. The method includes providing the pulsed signal to control power of a radio frequency (RF) signal that is generated by an RF generator. The power is controlled to be synchronous with the pulsed signal.

The arrival time of an asynchronous signal from an asynchronous domain at a synchronizer circuit of a synchronous domain is modified by injecting synchronous domain timing into an additional last stage of the asynchronous logic function generating the asynchronous signal. That reduces the probability of metastability by increasing the probability that the asynchronous signal will arrive at the synchronizer at a time that can guarantee the setup time for the flip-flop(s) of the synchronizer.

The arrival time of an asynchronous signal from an asynchronous domain at a synchronizer circuit of a synchronous domain is modified by injecting synchronous domain timing into an additional last stage of the asynchronous logic function generating the asynchronous signal. That reduces the probability of metastability by increasing the probability that the asynchronous signal will arrive at the synchronizer at a time that can guarantee the setup time for the flip-flop(s) of the synchronizer.

The present disclosure is directed towards systems and method for actively tuning a phase locked loop based on vibration excitation levels experienced by the phase locked loop. A bandwidth of the phase locked loop can be actively increased or decreased based upon a detected vibration level. In an embodiment, the phase locked loop includes a controllable oscillator, an output module, a filter module and a detector. The filter module can be configured to receive a bandwidth control signal to modify a bandwidth of the phase locked loop based on a vibration signal. In an embodiment, the vibration signal corresponds to a vibration level experienced by the phased locked loop. The detector can be configured to receive a PLL output signal from the output module and to receive a PLL input signal.

A clock generation circuit includes a control clock generation circuit and first and second clock synchronization circuits. The control clock generation circuit compares a reference voltage with first and second feedback clock signals to generate first and second control clock signals. The first clock synchronization circuit makes the first and second feedback clock signals transit in synchronization with the first and second control clock signals. The second clock synchronization circuit generates first and second phase clock signals in synchronization with the first feedback clock signal and the second feedback clock signal.

A charge pump circuit includes: a charge pump core circuit configured to generate an output voltage, an oscillator configured to provide a clock signal for the charge pump core circuit, and a feedback circuit configured to control the oscillator based on the output voltage, wherein the feedback circuit includes an inner loop.

A receiver includes: an A/D converter that performs an analog digital conversion of an input signal; an equalizer that equalizes an output from the A/D converter, eliminates inter code interference and obtains a data output; a timing recovery part that generates a recovery clock from the data output of the equalizer; a detector that detects the timing when an input signal varies from a no-signal state and has reached a predetermined threshold; and an initial phase setting part that sets as the initial phase of the recovery clock by the timing recovery part, a timing when the predetermined time has elapsed after the timing detected by the detector.

A receiver includes: an A/D converter that performs an analog digital conversion of an input signal; an equalizer that equalizes an output from the A/D converter, eliminates inter code interference and obtains a data output; a timing recovery part that generates a recovery clock from the data output of the equalizer; a detector that detects the timing when an input signal varies from a no-signal state and has reached a predetermined threshold; and an initial phase setting part that sets as the initial phase of the recovery clock by the timing recovery part, a timing when the predetermined time has elapsed after the timing detected by the detector.

Methods and systems are described for generating, at a plurality of delay stages of a local oscillator, a plurality of phases of a local oscillator signal, generating a loop error signal based on a comparison of one or more phases of the local oscillator signal to one or more phases of a received reference clock, generating a plurality of phase-specific quadrature error signals, each phase-specific quadrature error signal associated with a respective phase of the plurality of phases of the local oscillator signal, each phase-specific quadrature error signal based on a comparison of the respective phase to two or more other phases of the local oscillator signal, and adjusting each delay stage according to a corresponding phase-specific quadrature error signal of the plurality of phase-specific quadrature error signals and the loop error signal.