Systems and methods provide a fractional signal from a delta sigma modulator to a summer, a combination of an integer value and the fractional signal to a divider, and a divided clock signal from the divider in response to the combination and the input clock signal. The systems and methods also delay the divided clock signal in response to a truncation phase error and gain calibration factor from a calibration unit to provide an output clock signal having equal periods.

The disclosure relates to a radio frequency oscillator. The radio frequency oscillator includes a resonator circuit being resonant at an excitation of the resonator circuit in a differential mode and at an excitation of the resonator circuit in a common mode. The resonator circuit has a differential mode resonance frequency at the excitation in the differential mode, and the resonator circuit has a common mode resonance frequency at the excitation in the common mode. A first excitation circuit is configured to excite the resonator circuit in the differential mode to obtain a differential mode oscillator signal oscillating at the differential mode resonance frequency, and a second excitation circuit is configured to excite the resonator circuit in the common mode to obtain a common mode oscillator signal oscillating at the common mode resonance frequency.

Techniques are described that enables controlling the TNULL characteristic of a self-compensated oscillator by controlling the magnitude and direction of the frequency deviation versus temperature, and thus, compensating the frequency deviation.

Techniques are described that enables controlling the TNULL characteristic of a self-compensated oscillator by controlling the magnitude and direction of the frequency deviation versus temperature, and thus, compensating the frequency deviation.

Disclosed is an electronic device. Other various embodiments as understood from the specification are also possible. The electronic device may include an antenna, a communication module including a transceiver, and a control circuit. The control circuit may be configured to radiate a first signal generated from the transceiver through the antenna, to obtain at least part of a second signal obtained by combining a forward signal delivered from the communication module to the antenna and a reverse signal reflected from the antenna, and to determine a reflection coefficient for the antenna based on at least part of the first signal and at least part of the second signal.

A method for performing divided-clock phase synchronization in a multi-divided-clock system, an associated synchronization control circuit, an associated synchronization control sub-circuit and an associated electronic device are provided. The method may include: performing frequency division operations according to a source clock to generate a first divided clock and a second divided clock; performing phase relationship detection on the first divided clock according to the second divided clock to generate a phase relationship detection result signal; performing a logic operation on a first phase selection result output signal and the phase relationship detection result signal to generate a second phase selection result output signal; and outputting one of the second divided clock and an inverted signal of the second divided clock according to the second phase selection result output signal, for further use in a physical layer circuit.

A method for performing divided-clock phase synchronization in a multi-divided-clock system, an associated synchronization control circuit, an associated synchronization control sub-circuit and an associated electronic device are provided. The method may include: performing frequency division operations according to a source clock to generate a first divided clock and a second divided clock; performing phase relationship detection on the first divided clock according to the second divided clock to generate a phase relationship detection result signal; performing a logic operation on a first phase selection result output signal and the phase relationship detection result signal to generate a second phase selection result output signal; and outputting one of the second divided clock and an inverted signal of the second divided clock according to the second phase selection result output signal, for further use in a physical layer circuit.

A resonator circuit includes a transformer comprising a primary winding and a secondary winding. The primary winding is inductively coupled with the secondary winding. A primary capacitor is connected to the primary winding. The primary capacitor and the primary winding form a primary circuit. A secondary capacitor is connected to the secondary winding. The secondary capacitor and the secondary winding form a secondary circuit. The resonator circuit has a common mode resonance frequency at an excitation of the primary circuit in a common mode. The resonator circuit has a differential mode resonance frequency at an excitation of the primary circuit in a differential mode. The common mode resonance frequency is different from the differential mode resonance frequency.

A resonator circuit includes a transformer comprising a primary winding and a secondary winding. The primary winding is inductively coupled with the secondary winding. A primary capacitor is connected to the primary winding. The primary capacitor and the primary winding form a primary circuit. A secondary capacitor is connected to the secondary winding. The secondary capacitor and the secondary winding form a secondary circuit. The resonator circuit has a common mode resonance frequency at an excitation of the primary circuit in a common mode. The resonator circuit has a differential mode resonance frequency at an excitation of the primary circuit in a differential mode. The common mode resonance frequency is different from the differential mode resonance frequency.

According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.