The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a clock generator that includes a source clock generates a source clock signal at a low frequency. A clock multiplier multiplies the source clock signal by a predetermined factor to generate a high frequency clock signal. The high frequency clock signal is corrected by a time adjustment module by applying a compensation signal. The compensation signal is determined by a jitter measurement module, which uses both the high frequency clock signal and a jitter reference signal to determine the compensation signal. There are other embodiments as well.

Disclosed herein are related to a system and a method for synchronizing signal processing on audio channels. In one aspect, a system includes processors, each including an audio data input configured to receive audio data from multiple audio sources. In one aspect, each processor includes audio channels coupled to the audio data input, where each audio channel includes a corresponding processing chain configured to convert a sample rate of audio data from a corresponding audio source. Each processor may include a synchronization pulse generator configured to generate a corresponding synchronization pulse for each processing chain in response to a trigger pulse. The synchronization pulse generator may include a counter configured to generate an output having a phase based on a programmable initial condition of the counter, where the synchronization pulse for each processing chain is based on the counter output and a phase register value of the corresponding processing chain.

Disclosed herein are related to a system and a method for synchronizing signal processing on audio channels. In one aspect, a system includes processors, each including an audio data input configured to receive audio data from multiple audio sources. In one aspect, each processor includes audio channels coupled to the audio data input, where each audio channel includes a corresponding processing chain configured to convert a sample rate of audio data from a corresponding audio source. Each processor may include a synchronization pulse generator configured to generate a corresponding synchronization pulse for each processing chain in response to a trigger pulse. The synchronization pulse generator may include a counter configured to generate an output having a phase based on a programmable initial condition of the counter, where the synchronization pulse for each processing chain is based on the counter output and a phase register value of the corresponding processing chain.

The phase-synchronizing circuit according to the present disclosure includes: a signal source to output a signal; a signal separator to output part of the signal from the signal source as a transmission signal and receive a reflected signal of the transmission signal; a first phase controller to change a phase of the transmission signal from the signal separator according to a control signal; a signal reflector to pass the transmission signal from the first phase controller as an output signal and output part of the output signal as the reflected signal; and a phase comparator to receive part of the signal from the signal source as a reference signal, compare a phase of the reference signal with a phase of the reflected signal from the signal reflector, and output the control signal corresponding to a phase difference between the reference signal and the reflected signal to the first phase controller.

The phase-synchronizing circuit according to the present disclosure includes: a signal source to output a signal; a signal separator to output part of the signal from the signal source as a transmission signal and receive a reflected signal of the transmission signal; a first phase controller to change a phase of the transmission signal from the signal separator according to a control signal; a signal reflector to pass the transmission signal from the first phase controller as an output signal and output part of the output signal as the reflected signal; and a phase comparator to receive part of the signal from the signal source as a reference signal, compare a phase of the reference signal with a phase of the reflected signal from the signal reflector, and output the control signal corresponding to a phase difference between the reference signal and the reflected signal to the first phase controller.

The present disclosure relates to a voltage controlled oscillator comprising a plurality of oscillator cores magnetically coupled in series.

An all-digital phase-locked loop (ADPLL) circuit and a calibration method thereof are provided. The ADPLL circuit includes a digitally controlled oscillator (DCO) circuit, a phase detector circuit, and a calibration circuit coupled between the DCO circuit and the phase detector circuit. The DCO circuit generates a clock signal according to a frequency control signal. The phase detector circuit generates a phase error value according to a reference signal and the clock signal. More particularly, after the ADPLL circuit performs a locking operation for a period of time, the frequency control signal is tied at a locked value which is obtained when the ADPLL circuit performs the locking operation, and the calibration circuit may modify a current of at least one current source within the DCO circuit according to the phase error value.

According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

The present disclosure is directed to a digital phase-locked loop frequency synthesizer including: a digitally controlled voltage-controlled oscillator (DCO); a reference oscillator; a digital phase detector; a DCO control module comprising a plurality of registers each arranged to control the frequency of the signal with a predetermined resolution; a first feedback loop arranged to provide a first feedback path between the output of the DCO and the digital phase detector; and a second feedback loop arranged to provide a second feedback path between the first register output and the second register input, the second feedback loop comprising an adder module arranged to change a value of the second register based on the first register output to maximize a DCO frequency output range provided by the first register.