This disclosure provides a split-path equalizer and a clock recovery circuit. More particularly, clock recovery operation is enhanced, particularly at high-signaling rates, by separately equalizing each of a data path and an edge path. In specific embodiments, the data path is equalized in a manner that maximizes signal-to-noise ratio and the edge path is equalized in a manner that emphasizes symmetric edge response for a single unit interval and zero edge response for other unit intervals (e.g., irrespective of peak voltage margin). Such equalization tightens edge grouping and thus enhances clock recovery, while at the same time optimizing data-path sampling. Techniques are also disclosed for addressing split-path equalization-induced skew.

This disclosure provides a split-path equalizer and a clock recovery circuit. More particularly, clock recovery operation is enhanced, particularly at high-signaling rates, by separately equalizing each of a data path and an edge path. In specific embodiments, the data path is equalized in a manner that maximizes signal-to-noise ratio and the edge path is equalized in a manner that emphasizes symmetric edge response for a single unit interval and zero edge response for other unit intervals (e.g., irrespective of peak voltage margin). Such equalization tightens edge grouping and thus enhances clock recovery, while at the same time optimizing data-path sampling. Techniques are also disclosed for addressing split-path equalization-induced skew.

According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

An optoelectronic oscillator (OEO) including a drift compensation circuit is provided. The OEO includes a set of optical domain components communicatively coupled with a set of RF domain components. The RF domain components include a mode selection filter, a phase locked loop (PLL) and a drift compensation circuit communicatively coupled between the mode selection filter and the PLL. The mode selection filter provides a mode selection result to the drift compensation circuit. The drift compensation circuit phase modulates the mode selection result in a vector based coordinate system to maintain a drift compensated mode selection result within a locking bandwidth of the PLL, and to minimize phase shifting from accumulating phase drift. The PLL detects a phase difference between the drift compensated mode selection result and a reference signal, for use in maintaining the PLL in a phase lock with the reference signal, in particular over wide operational temperature ranges.

A switching method, including: electrically coupling a switching circuit to a first impedance circuit, a second impedance circuit, a positive terminal of a frequency generation circuit and a negative terminal of the frequency generation circuit; adjusting an impedance value of the second impedance circuit according to a first clock signal and a second clock signal outputted by the frequency generation circuit; periodically conducting the negative terminal to one of the first impedance circuit and the second impedance circuit by a first switching unit of the switching circuit; and periodically conducting the positive terminal to the other one of the first impedance circuit and the second impedance circuit by a second switching unit of the switching circuit.

Clock circuits designed to compensate for supply voltage fluctuations (e.g., supply voltage droops) in central processing units (CPUs) are described. The clock circuits described herein involve reducing the clock frequency in response to a decrease to the supply voltage to a value that is approximately equal (or below) to the maximum operating frequency of the CPU at that particular supply voltage. The clock circuits described herein may include a frequency locked loops (FLL). Such FLLs may be designed to lock to a reference frequency when the supply voltage is approximately constant and to deviate from the reference frequency in response to variations in the supply voltage. In some embodiments, an FLL operates in the same supply voltage domain as the CPU.

A fast start-up crystal oscillator (XO) and a fast start-up method thereof are provided. The fast start-up XO may include a XO core circuit, a frequency synthesizer, and a fast start-up interfacing circuit, wherein the frequency synthesizer may include a voltage control oscillator (VCO) and a divider. The XO core circuit generates a XO signal having a XO frequency. The VCO generates a VCO clock having a VCO frequency, and the divider generates a divided clock having a divided frequency, wherein the VCO frequency is divided by a divisor of the divider to obtain the divided frequency. The fast start-up interfacing circuit transmits the divided clock to the XO core circuit, and then generates a reference clock having the XO frequency according to the XO signal. More particularly, the VCO frequency is calibrated according to the reference clock, in order to make the divided frequency approach the XO frequency.

A fast start-up crystal oscillator (XO) and a fast start-up method thereof are provided. The fast start-up XO may include a XO core circuit, a frequency synthesizer, and a fast start-up interfacing circuit, wherein the frequency synthesizer may include a voltage control oscillator (VCO) and a divider. The XO core circuit generates a XO signal having a XO frequency. The VCO generates a VCO clock having a VCO frequency, and the divider generates a divided clock having a divided frequency, wherein the VCO frequency is divided by a divisor of the divider to obtain the divided frequency. The fast start-up interfacing circuit transmits the divided clock to the XO core circuit, and then generates a reference clock having the XO frequency according to the XO signal. More particularly, the VCO frequency is calibrated according to the reference clock, in order to make the divided frequency approach the XO frequency.

A clock generation circuit has an injection-locked oscillator, a frequency doubler circuit, low pass filters and a calibration circuit. The injection-locked oscillator has an input coupled to a half-rate clock signal. The frequency doubler circuit has inputs coupled to outputs of the injection-locked oscillator. Each of the low pass filters has an input coupled to one of a plurality of outputs of the frequency doubler circuit. The calibration circuit includes comparison logic that receives outputs of the low pass filters. The calibration circuit has an output coupled to a control input of a source of a supply current in the injection-locked oscillator. In one example, the source of the supply current is a current digital to analog converter.