A signal distribution system includes: a first signal divider arranged to generate a first output oscillating signal according to a first input oscillating signal; a second signal divider arranged to generate a second output oscillating signal according to the first input oscillating signal; a first transmitting channel coupled to the first signal divider and the second divider for transmitting the first input oscillating signal to the first signal divider and the second signal divider; and a second transmitting channel coupled to the first signal divider and the second divider for transmitting a second input oscillating signal to the first signal divider and the second signal divider; wherein the first input oscillating signal has a first frequency, the second input oscillating signal has a second frequency, and the second frequency is smaller than the first frequency.

A signal distribution system includes: a first signal divider arranged to generate a first output oscillating signal according to a first input oscillating signal; a second signal divider arranged to generate a second output oscillating signal according to the first input oscillating signal; a first transmitting channel coupled to the first signal divider and the second divider for transmitting the first input oscillating signal to the first signal divider and the second signal divider; and a second transmitting channel coupled to the first signal divider and the second divider for transmitting a second input oscillating signal to the first signal divider and the second signal divider; wherein the first input oscillating signal has a first frequency, the second input oscillating signal has a second frequency, and the second frequency is smaller than the first frequency.

A spread spectrum clock generator includes a phase comparator that compares a reference clock with a feedback clock, a low-pass filter that passes a predetermined low-frequency component, a phase lock loop that includes a voltage-controlled oscillator generating an output clock whose frequency corresponds to the filtered signal, a triangular wave controller that generates a triangular wave signal for frequency-modulating the spread spectrum clock based on the output clock, a delay controller that generates the feedback clock by controlling delay of the output clock based on the triangular wave signal, a first counter that counts the output clock and output a first count value, a second counter that counts the reference clock and output a second count value, and a phase error correction circuit that compares the first count value with the second count value and corrects phase error of the output clock.

Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

Provided are a digitally controlled oscillator and an electronic device including the digitally controlled oscillator. The digitally controlled oscillator includes a digital control unit and a power control oscillation unit. The digital control unit compensates for a difference between a feedback signal of an output power and a reference power set based on an input digital control signal and outputting an output power. The power control oscillation unit receives a signal related to the output power, and generates an output clock having an oscillation frequency in response to the signal related to the output power.

Methods, devices and computer-readable mediums for clock synchronization are provided. The methods include receiving a synchronizing clock in a unit clock cycle of a measuring clock, calibrating position information of a rising edge of the synchronizing clock in the unit clock cycle, determining a phase difference between the measuring clock and the synchronizing clock in the unit clock cycle based on the calibrated position information, and compensating a photon time in the unit clock cycle with the determined phase difference as a time compensation value.

Methods, devices and computer-readable mediums for clock synchronization are provided. The methods include receiving a synchronizing clock in a unit clock cycle of a measuring clock, calibrating position information of a rising edge of the synchronizing clock in the unit clock cycle, determining a phase difference between the measuring clock and the synchronizing clock in the unit clock cycle based on the calibrated position information, and compensating a photon time in the unit clock cycle with the determined phase difference as a time compensation value.

A method for a node device to enter or exit a power-saving mode and a node device are disclosed. The method for a node device to enter a power-saving mode includes: the node device detecting characteristics of a reverse power supply signal provided by a customer premise equipment, and if a condition of entering a power-saving mode is satisfied, the node device entering the power-saving mode. The method for a node device to exit a power-saving mode includes: the node device in a power-saving mode exiting the power-saving mode after detecting that a customer premise equipment starts reverse power supply to the node device. The node device includes a reverse power supply unit, a power source unit, a control unit, and a transceiver unit.

A method for calibrating a mixer, an apparatus using the calibrated mixer, and a method for using the apparatus to calibrate another mixer are disclosed. The method includes coupling a first RF signal characterized by a first timezero phase and a first RF frequency to the RF signal input. The method includes (a) coupling a first LO signal characterized by a first LO frequency and a first LO timezero phase to the LO signal input terminal; (b) determining an IF tone timezero phase of a tone from the IF signal output corresponding to the first LO signal; and (c) determining a first after LO signal path timezero phase from the IF tone and first LO timezero phase. Steps (a), (b), and (c) are repeated for second and third LO signals. An LO phase change as a function of frequency introduced by the LO signal path is then determined.

A semiconductor apparatus includes a control circuit and a level shifter. The control circuit is configured to output a power control signal for activating a data input/output circuit operated by a first voltage when the first voltage is higher than a first set voltage and a second voltage is higher a second set voltage. The level shifter configured to receive the power control signal and lower operating voltages of devices including a plurality of transistors with a thin gate insulating layer based on the power control signal.