An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.

A system for converting digital data into a modulated optical signal, comprises an electrically controllable device having M actuating electrodes. The device provides an optical signal that is modulated in response to binary voltages applied to the actuating electrodes. The system also comprises a digital-to-digital converter that provides a mapping of input data words to binary actuation vectors of M bits and supplies the binary actuation vectors as M bits of binary actuation voltages to the M actuating electrodes, where M is larger than the number of bits in each input data word. The digital-to-digital converter is enabled to map each digital input data word to a binary actuation vector by selecting a binary actuation vector from a subset of binary actuation vectors available to represent each of the input data words.

An embodiment target time comparison circuit corresponding to a target approximate voltage range among 2.sup.K time comparison circuits in a second comparison circuit compares a comparison operation time difference included in voltage comparison results regarding two adjacent approximate voltage ranges that are vertically adjacent to the target approximate voltage range with 2.sup.L reference times corresponding to 2.sup.L specific voltage ranges and generates a target binary code of L bits indicating a target specific voltage range including the held voltage from the obtained time comparison results.

A subsystem configured to implement an analog to digital converter that includes a high speed comparator with an embedded reference voltage level that functions as a calibrated threshold. A calibration element applies power to a reference voltage system. The calibration element then selects a differential analog voltage and applies the differential analog voltage to the inputs of the comparator. A digitally coded signal then configures an array of switches that connect complements of integrated resistors to each input of the comparator so that the switching point of the comparator occurs coincident with the applied differential analog reference voltage, nulling out the effect of the applied differential analog voltage and comparator errors. The calibration element then removes power from the reference voltage system. As a result, the comparator is configured with an embedded threshold that equals the differential analog reference voltage.

The disclosure is directed to low-power high-resolution analog-to-digital converter (ADCs) circuits implemented with a delta-sigma modulators (DSMs). The DSM includes a single-bit, self-oscillating digital to analog converter (SB-DAC) and a dual-slope integrating quantizer that may replace an N-bit quantizer found in a conventional DSM. The integrating quantizer of this disclosure oscillates after quantization because the SB-DAC in the feedback path directly closes the DSM loop. The integrating quantizer circuit includes a switch at the input and two phases per sample cycle. During the first phase the switch sends an input analog signal to an integrator. During the second phase, the switch sends the feedback signal from the output of the self-oscillating SB-DAC to the integrator. The input to the SB-DAC may be output from a clocked comparator.

A system is described for time synchronizing digitized measurement signals, such as vibration signals. The digitized signals, which are acquired asynchronously by multiple distributed measurement units, indicate the operational condition of a machine or a process. To measure the phase of the digitized signals relative to a pulse tachometer input, the time between the leading edge of the tachometer pulse and the digitized samples is measured. To achieve phase-coherent synchronization across the distributed measurement units, a local synchronization signal is embedded into the data produced by the measurement units. The systems uses the synchronization signal to align the data in post processing, which phase aligns the data and aligns the data in absolute time. The synchronization signal may be encoded with a timestamp to provide additional timing information.

A system is described for time synchronizing digitized measurement signals, such as vibration signals. The digitized signals, which are acquired asynchronously by multiple distributed measurement units, indicate the operational condition of a machine or a process. To measure the phase of the digitized signals relative to a pulse tachometer input, the time between the leading edge of the tachometer pulse and the digitized samples is measured. To achieve phase-coherent synchronization across the distributed measurement units, a local synchronization signal is embedded into the data produced by the measurement units. The systems uses the synchronization signal to align the data in post processing, which phase aligns the data and aligns the data in absolute time. The synchronization signal may be encoded with a timestamp to provide additional timing information.

The present invention pertains to a high-speed successive approximation analog-to-digital converter of two bits per circle, includes three switches, two capacitor arrays, three comparators, an encoding circuit, a first switch array corresponding to the first capacitor array, a second switch array corresponding to the second capacitor array, a shifting register and a digital correction unit. The analog-to-digital converter, featuring doubled speed, realizes a successive approximation process without any fault when a high-bit large capacitor is unsettled. Thus no redundancy bit capacitor is required to compensate for unsettled pre-stage large capacitor. By using the encoding circuit, a thermometer code is converted into a binary code effectively, and inherent errors of comparators are reduced by the randomization of three comparators.

The objective of the present invention is to make it possible to execute each of a plurality of application programs without taking into account the addresses of the programs. A microcomputer (100) is provided with: a program memory (108) which stores a plurality of microphone programs executed by a digital signal processing circuit (104); an address control circuit (109) which controls addresses in the program memory; a program address register (110) which stores the addresses of the microphone programs; and a program size register (111) which stores the sizes of the microphone programs. The address control circuit (109) calculates the addresses in the program memory on the basis of the program address register (110) and the program size register (111).

A wide band continuous time delta-sigma modulator implements a time interleaved quantization processing operation. The modulator may provide for an inherent finite impulse response filtering in the feedback loop. Additionally, further finite impulse response filtering in each time interleaved feedback path may be provided.