There is disclosed herein integrated circuitry,comprising a signal path connected to a connection pad, for connection to external circuitry; and a termination circuit connected between the signal path and a voltage reference, wherein the termination circuit comprises a resistor and an inductor. The resistor and the inductor are connected together so as to compensate for parasitic capacitance associated with the connection pad. The signal path may carry an output signal from high-speed circuitry such as digital-to-analogue converter circuitry.

According to one example embodiment, an image sensor is configured to operate in a plurality of operation modes. The image sensor includes a pixel array including unit pixels configured to generate an analog image signal from incident light, a readout circuit configured to generate a digital image signal by converting the analog image signal, and a control module configured to generate control signals for controlling operations of the pixel array and the readout circuit according to an operation mode of the image sensor. A first power voltage for driving the image sensor when the operation mode of the image sensor is an image recognition mode for recognizing a body of a user of the image sensor, is lower than a second power voltage for driving the image sensor when the operation mode of the image sensor is an image capture mode for capturing images by the user.

An integrated constant time delay circuit utilized in continuous-time (CT) analog-to-digital converters (ADCs) can be implemented with an RC lattice structure to provide, e.g., a passive all-pass lattice filter. Additional poles created by decoupling capacitors can be used to provide a low-pass filtering effect in some embodiments. A Resistor-Capacitor “RC” lattice structure can be an alternative to a constant-resistance Inductor-Capacitor “LC” lattice implementation. ADC architectures benefit from the RC implementation, due to its ease of impedance scaling and smaller area.

A cyclic analog to digital converter for digitizing an output from a photoplethysmography sensor has a buffer amplifier for setting a voltage of the feedback capacitance. Additionally, digital averaging circuit is preferably provided for averaging the digital output from the cyclic analog to digital converter for the several conversions. Finally, voting logic is additionally provided for declaring the digital bits based on successive comparisons by the one or more comparators.

An analog-to-digital converter (ADC) configured to convert an analog signal to digital bits. The ADC includes a plurality of sub-ADCs that are cascaded in a pipeline. Each sub-ADC may be configured to sample an input signal that is fed to each sub-ADC and convert the sampled input signal to a pre-configured number of digital bits. Each sub-ADC except a last sub-ADC in the pipeline is configured to generate a residue signal and feed the residue signal as the input signal to a succeeding sub-ADC in the pipeline. At least one sub-ADC is configured to determine a most-significant bit (MSB) of the pre-configured number of digital bits while the input signal is sampled. The ADC may include a plurality of residue amplifiers for amplifying a residue signal. The sub-ADCs may be successive approximation register (SAR) ADCs or flash ADCs.

An all-digital voltage monitor (ADVM) generates a multi-bit output code that changes in proportion to a voltage being monitored, by leveraging the voltage impact on a gate delay. ADVM utilizes a simple delay chain, which receives a clock-cycle-long pulse every clock cycle, such that the monitored supply voltage is sampled for one full cycle every cycle. The outputs of all delay cells of the delay chain collectively represents a current voltage state as a digital thermometer code. In AVDM, a voltage droop event thus results in a decrease in the output code from a nominal value, while an overshoot results in an increase in the output code.

Embodiments include applying neural network technologies to encoding/decoding technologies by training and encoder model and a decoder model using a neural network. Neural network training is used to tune a neural network parameter for the encoder model and a neural network parameter for the decoder model that approximates an objective function. The common objective function may specify a minimized reconstruction error to be achieved by the encoder model and the decoder model when reconstructing (encoding then decoding) training data. The common objective function also specifies for the encoder and decoder models, a variable f representing static aspects of the training data and a set of variables z1:T representing dynamic aspects of the training data. During runtime, the trained encoder and decoder models are implemented by encoder and decoder machines to encode and decoder runtime sequences having a higher compression rate and a lower reconstruction error than in prior approaches.

Embodiments include applying neural network technologies to encoding/decoding technologies by training and encoder model and a decoder model using a neural network. Neural network training is used to tune a neural network parameter for the encoder model and a neural network parameter for the decoder model that approximates an objective function. The common objective function may specify a minimized reconstruction error to be achieved by the encoder model and the decoder model when reconstructing (encoding then decoding) training data. The common objective function also specifies for the encoder and decoder models, a variable f representing static aspects of the training data and a set of variables z1:T representing dynamic aspects of the training data. During runtime, the trained encoder and decoder models are implemented by encoder and decoder machines to encode and decoder runtime sequences having a higher compression rate and a lower reconstruction error than in prior approaches.

The present disclosure provides a DC power supply system, comprising: a first power supply circuit and a second power supply circuit, each power supply circuit comprises a phase-shifting transformer and an AC-DC conversion circuit; and a bidirectional electronic switch electrically coupled between the output end of the first power supply circuit and the output end of the second power supply circuit, wherein the bidirectional electronic switch is configured to transmit power between the output end of the first power supply circuit and the output end of the second power supply circuit depend on the voltage difference of the two output voltages.

A circuit for receiving serial data. In some embodiments, the circuit has an input for receiving an analog input signal, and includes a first sampler for sampling the analog input signal relative to a first reference voltage, a second sampler for sampling the analog input signal relative to a second reference voltage, and a reference voltage control circuit. The second reference voltage may have a sign opposite to that of the first reference voltage; and the reference voltage control circuit may be configured to adjust the first reference voltage or the second reference voltage, based on a first sample of the analog input signal, the first sample having been taken at a sampling time corresponding to a one bit, in the serial data, preceded by a one bit and followed by a one bit.