A pulse signal corresponding to rotation of an imaging core is input, and a repetition frequency of the input pulse signal is converted in accordance with the number of radially-aligned lines of an ultrasound tomographic image. Based on the pulse signal of which the repetition frequency has been converted, a drive signal for an ultrasound transceiver is generated to obtain an ultrasound tomographic image with the number of lines. A valid pulse is determined in accordance with the number of lines from the pulse signal of which the repetition frequency has been converted. A signal having a pulse train selected, based on the valid pulse from a pulse signal representing a cycle of a light source of light for interfering with the light from an optical transceiver is generated as a pulse signal representing a timing of sampling of an optical coherence signal for generating an optical tomographic image.

There is described a hybrid ADC device for converting an analog input signal (Vin) into a digital output signal (Vout), the device comprising a first ADC circuit configured to receive the analog input signal (Vin) and convert it into a first digital signal (Y0); a DAC circuit configured to receive the first digital signal and convert it into a first analog signal; a delay circuit configured to delay the analog input signal; a first combiner configured to generate an analog residual signal by subtracting the first analog signal from the delayed analog input signal; a second ADC circuit configured to receive the residual analog signal and convert it into a second digital signal (Y1); a filter circuit configured to receive the first digital signal and output a filtered first digital signal (Y0′), the filter circuit having a transfer function corresponding to a combined transfer function of the DAC circuit and the second ADC circuit; and a second combiner configured to generate the digital output signal (Vout) by adding the second digital signal and the filtered first digital signal, wherein the first ADC circuit comprises an anti-aliasing filter. Furthermore, a corresponding method and an automobile radar system are described.

Aspects of the technology described herein relate to control circuitry configured to turn on and off the ADC driver. In some embodiments, the control circuitry is configured to turn on and off the ADC driver in synchronization with sampling activity of an ADC, in particular based on when an ADC is sampling. The control circuitry may be configured to turn on the ADC driver during the hold phase of the ADC a time period before the track phase and to turn off the ADC driver during the hold phase a time period after the track phase. In some embodiments, the control circuitry is configured to control a duty cycle of the ADC driver turning on and off. In some embodiments, the control circuitry is configured to control a ratio between an off current and an on current in the ADC driver.

Aspects of the technology described herein relate to control circuitry configured to turn on and off the ADC driver. In some embodiments, the control circuitry is configured to turn on and off the ADC driver in synchronization with sampling activity of an ADC, in particular based on when an ADC is sampling. The control circuitry may be configured to turn on the ADC driver during the hold phase of the ADC a time period before the track phase and to turn off the ADC driver during the hold phase a time period after the track phase. In some embodiments, the control circuitry is configured to control a duty cycle of the ADC driver turning on and off. In some embodiments, the control circuitry is configured to control a ratio between an off current and an on current in the ADC driver.

This application provides example signal processing apparatus and example signal processing method. One example signal processing apparatus includes a sampling unit, a beam combiner, and an optical resonator. The sampling unit is connected to the beam combiner, and the beam combiner is connected to the optical resonator. The sampling unit is configured to sample an analog signal by using an optical pulse signal to output a sampled optical pulse signal. The beam combiner is configured to combine the sampled optical pulse signal and a multi-wavelength optical signal into a first optical signal. The optical resonator is configured to perform resonance based on the first optical signal to output a second optical signal in the first optical signal, where a wavelength of the second optical signal is equal to a resonant wavelength of the optical resonator.

The digital-output temperature sensor includes a temperature sensor circuit, a current mirror circuit which makes a mirror current of a temperature detection current flow and pulls in a mirror current of a reference current to thereby output a first difference current from a first output node and output a second difference current from a second output node, a chopping circuit, and an A/D conversion circuit. The chopping circuit performs a chopping operation of making the mirror current of the reference current flow in a second state through a transistor of the current mirror circuit through which the mirror current of the temperature detection current flows in a first state, and making the mirror current of the temperature detection current flow in the second state through the transistor of the current mirror circuit through which the mirror current of the reference current flows in the first state.

Disclosed herein are devices, systems, and methods for improved demodulation. In one embodiment, a demodulator includes an input port configured to receive an analog input signal having a first frequency spectrum, a delta-sigma modulator electrically coupled with the input port, a digital downconverter electrically coupled with the delta-sigma modulator, and a filter electrically coupled with the digital downconverter. The filter is configured for a passband having a second frequency spectrum. The demodulator also includes an output port electrically coupled with the filter. The output port is configured to provide an output signal having the second frequency spectrum.

Technologies relating to analog-to-analog quantizers with an intrinsic Rectified Linear Unit (ReLU) function designed for in-memory computing are disclosed. An apparatus, in some implementations, includes: a DAC; a first crossbar connected to the DAC; a first analog quantizer connected to the first crossbar; a buffer connected to the first analog quantizer; a second crossbar connected to the buffer; and an ADC connected to the second crossbar.

A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. A number of capacitive digital analog converter (CDAC) cells of a power amplifier can be sized to provide defined power signals along a signal path. In response to an optimization component that is coupled to a CDAC cell of the plurality of CDAC cells operating in a high efficiency enable mode and the CDAC cell being powered off in an off mode, the optimization component can increase a power efficiency of the power amplifier by reducing an impedance of an output capacitor of the CDAC cell.

Analog to digital conversion circuitry has an input sampling buffer, which has an input sampling capacitor for sampling an analog signal. The conversion circuitry also has a successive-approximation-register analog to digital converter (SAR-ADC) which converts the sampled analog signal to a digital signal. The input sampling buffer has an amplifier and a gain-control capacitor, and has an amplification configuration and an error-feedback configuration. In the amplification configuration, the input sampling capacitor is coupled to the amplifier and gain-control capacitor, with the gain-control capacitor connected in feedback with the amplifier, for applying gain to the sampled analog signal. In the error-feedback configuration, the gain-control capacitor is decoupled from the input sampling capacitor and receives a residue voltage from the SAR-ADC, such that the level of the analog signal determined in the amplification configuration varies depending on the residue voltage received onto the gain-control capacitor in the error-feedback configuration.