A circuit includes a transistor, a signal generating circuit and a noise sensing circuit. The signal generating circuit is arranged to provide an input signal. The noise sensing circuit is coupled to the transistor and the signal generating circuit, and the noise sensing circuit is arranged for receiving the input signal provided by the signal generating circuit to generate an output signal to the transistor, wherein a signal component of the output signal generated by the noise sensing circuit cancels out a signal component of the input signal provided by the signal generating circuit, and the output signal and the input signal have opposite polarities.

This disclosure relates to a current-to-digital converter suitable for wide-ranging current sensing applications. In particular, the current-to-digital converter comprises a delta-sigma analogue-to-digital converter which utilizes a successive-approximation-register to control a modulation of the sensed current so that the digital conversion of the modulated sensed current by the delta-sigma analogue-to-digital converter may be done with high precision.

A sigma delta (SD) pulse-width modulation (PWM) loop includes a loop filter implementing a linear transfer function to generate a loop filter signal, wherein the loop filter is configured to receive an input signal and a first feedback signal and generate the loop filter signal based on the input signal, the first feedback signal, and the linear transfer function; and a hysteresis comparator coupled to an output of the loop filter, the hysteresis comparator configured to receive the loop filter signal and generate a sigma delta PWM signal based on the loop filter signal, wherein the first feedback signal is derived from the sigma delta PWM signal.

An apparatus comprises a sigma-delta analog-to-digital converter (ADC) circuit configured to convert an analog input signal to a digital value. The sigma-delta ADC circuit includes a loop filter circuit including at least one loop filter amplifier, a flash ADC circuit including multiple comparators, and a bias control circuit configured to change a biasing of the at least one loop filter amplifier according to outputs of the multiple comparators of the flash ADC circuit.

A method and an apparatus are provided for improving a carrier to noise density ratio (CNO) of a matched filter. A signal is received at a signal register of the matched filter. A local code is received at a local code register and a nulling register of the matched filter. An adder tree of the matched filter correlates the signal register and the local code register with respect to the nulling register to obtain a correlation result. The nulling register prevents high frequency samples of the signal register from affecting the correlation result.

A delta-sigma modulator is provided with: a loop filter 30; a quantizer 36 that generates quantized data on the basis of an output from the loop filter 30; an internal path 42 connected to the loop filter 30 or the quantizer 36; and a compensator 38 that provides, to the internal path 42, a compensation signal for compensating for distortion that occurs in a frequency component at a target frequency, the frequency component being among frequency components of a pulse train corresponding to the quantized data.

A digital PWM modulator modulates a digital input signal to drive a PWM signal to a PWM DAC susceptible to introducing inter-symbol interference (ISI) in small PWM edge separation presence causing audio THDN degradation. A multi-bit quantizer switches from a first to second mode when the input signal rises above a threshold. The quantizer quantizes the input signal into a quantized output signal, each sample of which has a code selected from respective first and second quantization code sets. The second set, relative to the first set, causes the digital PWM signal to have increased edge separation to reduce the ISI at high input levels. The first set includes small magnitude codes relative to the second set to reduce quantization noise at low input levels. The threshold is sufficiently low to cause the quantized output signal to be dominated by small codes when operating in the first mode.

A digital control circuitry for a MEMS gyroscope is provided. The digital control circuitry comprises a digital primary loop circuitry configured to process a digitized primary signal, a digital secondary loop circuitry configured to process a digitized secondary signal and a digital phase shifting filter circuitry configured to generate two phase shifted demodulation signals from the digitized primary signal. The digital secondary loop is configured to demodulate the digitized secondary signal using the two phase shifted demodulation signals.

An analog to digital converter (ADC) that is configured to service a photo-diode includes a capacitor and a self-referenced latched comparator. The capacitor produces a photo-diode voltage based on charging by a photo-diode current associated with the photo-diode and a digital to analog converter (DAC) source current and/or a DAC sink current. The self-referenced latched comparator generates a first digital signal that is based on a difference between the photo-diode voltage and a threshold voltage associated with the self-referenced latched comparator. Also, one or more processing modules executes operational instructions to process the first digital signal to generate a second digital signal and/or a third digital signal. An N-bit DAC generates the DAC source current based on the second digital signal, and an M-bit DAC generates the DAC sink current based on the third digital signal. The DAC source current and/or the DAC sink current tracks the photo-diode current.

Circuitry and techniques are described herein for performing accurate and low power conversion of an analog value into a digital value. According to some aspects, this disclosure describes a successive approximation register (SAR) analog to digital converter (ADC). According to some aspects the SAR ADC comprises an active integrator between a sample and hold stage and a comparator stage. The active integrator operates differently dependent on whether the SAR ADC is operated in a sample phase or a conversion phase. According to other aspects, the SAR ADC utilizes a ring oscillator-based comparator to compare a sampled analog input value to a plurality of reference values to determine a digital value representing the analog value.