First and second external terminals are connected to high-voltage and low-voltage terminals, respectively, of a direct-current voltage source circuit in which first and second direct-current voltage sources are connected in series. A third external terminal is connected to a connecting point between the first and second direct-current voltage sources. A first switching element is connected between the first and fourth external terminals. A second switching element is connected between the fourth and second external terminals. A first AC switch unit includes third and fourth switching elements connected in inverse series between the third and fourth external terminals. A second AC switch unit includes fifth and sixth switching elements connected in inverse series between the third and fourth external terminals. The first and second AC switch units are connected in parallel. The first and second switching elements and the first and second AC switch units are incorporated in one module.

First and second external terminals are connected to high-voltage and low-voltage terminals, respectively, of a direct-current voltage source circuit in which first and second direct-current voltage sources are connected in series. A third external terminal is connected to a connecting point between the first and second direct-current voltage sources. A first switching element is connected between the first and fourth external terminals. A second switching element is connected between the fourth and second external terminals. A first AC switch unit includes third and fourth switching elements connected in inverse series between the third and fourth external terminals. A second AC switch unit includes fifth and sixth switching elements connected in inverse series between the third and fourth external terminals. The first and second AC switch units are connected in parallel. The first and second switching elements and the first and second AC switch units are incorporated in one module.

An example method for forming a data-bearing medium in accordance with aspects of the present disclosure includes setting variables associated with the data-bearing medium, the variables comprising a bit length of a payload, a row-to-row offset and an interleave period, identifying a standard form of the payload, the standard form being a circularly shifted version of the payload, generating a phase code based on the variables, and arranging rows of the data-bearing medium with the standard form of the payload and the phase code based on the interleave period.

Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

In one embodiment, a computer program product for providing header protection in magnetic tape recording includes a computer readable storage medium having program instructions embodied therewith, the program instructions readable by a processor to cause the processor to: calculate or obtain, by the processor, codeword interleave designation (CWID) parity for all CWIDs in a codeword interleave (CWI) set header, the CWID parity including error correction coding (ECC) parity, and store, by the processor, the CWID parity to a magnetic tape in one or more fields which are repeated for each CWI header in the CWI set header without using reserved bits in the CWI set header to store the CWID parity. Other systems and methods for providing header protection in magnetic tape recording are described in more embodiments.

This application relates to a codeword synchronization method, a chip, a network device, and a system. The codeword synchronization method includes: receiving a first data sequence, where the first data sequence includes a plurality of bits, and a codeword in the first data sequence includes extension information for verifying the codeword; selecting at least one group of bits from the plurality of bits as the extension information to perform verification, and determining a candidate bit in the plurality of bits based on a result of the verification; and determining a synchronization position based on the candidate bit, where the synchronization position indicates a start position of the codeword that is in the first data sequence.