In artificial neural networks, and other similar applications, there is typically a large amount of data involved that is considered sparse data. Due to the large size of the data involved in such applications, it is helpful to compress the data to save bandwidth resources when transmitting the data and save memory resources when storing the data. Introduced herein is a compression technique that selects elements with significant values from data and restructures them into a structured sparse format. By generating metadata that enforces the structured sparse format and organizing the data according to the metadata, the introduced technique not only reduces the size of the data but also consistently places the data in a particular format. As such, hardware can be simplified and optimized to process the data much faster and much more efficiently than the conventional compression techniques that rely on a non-structured sparsity format.

The present disclosure generally relates to a method and device for simultaneously decoding data. Rather than sending data to be decoded to a single decoder, the data can be sent to multiple, available decoders so that the data can be decode in parallel. The data decoded from the first decoder that completes decoding of the data will be delivered to the host device. All remaining decoded data that was decoded in parallel will be discarded. The decoders operating simultaneously in parallel can operate using different parameters such as different calculation precision (power levels). By utilizing multiple decoders simultaneously in parallel, the full functionality of the data storage device's decoding capabilities are utilized without increasing latency.

Systems or methods for losslessly compressing data received from sensors, such as photon counters, are disclosed. An integer representation of a sensor reading is received from a sensor. The integer representation is combined with additional integer representations from each of a plurality of additional sensors into a single integer value. The single integer value is then stored as an element of an integer array that represents a predefined sample interval.

A decoding circuit and a chip are disclosed. The decoding circuit includes, connected in a sequence, a charge/discharge unit, a capacitor and a conversion unit. The charge/discharge unit is able to charge and discharge the capacitor, and a ratio of a total time required to transfer any amount of charge into the capacitor to a total time required to transfer the same amount of charge from the capacitor is a predetermined value. The conversion unit is configured to output a third level when a voltage on the capacitor exceeds a predetermined voltage and to otherwise output a fourth level. This arrangement alleviates the computational burden of an MCU, eliminates any adverse effect of noise in a transmitted signal, allows an extended effective transmission distance when using an HBS protocol and is self-adaptive to signals transmitted at different clock rates, thus solving the problems with the prior art including heavy MCU computational burden, a tradeoff between error correction and transmission distance and insufficient adaptiveness to signals transmitted at different clock rates.

The present disclosure provides a data encoding method, a decoding method, a related device, and a storage medium. The data encoding method first passes a first bit stream of an original encoded data through a logical operation to obtain a second bit stream. Then, through signal determination, negating processing, and insertion of corresponding flag bit, encoded data having a certain jump amplitude is obtained. A problem that signal is prone to error in transmission process is solved, reliability of coding is improved, and signal transmission is facilitated.

Systems and methods for encoding and decoding neural network data is provided. A method includes: receiving a neural network representation (NNR) bitstream including a group of NNR units (GON) that represents an independent neural network with a topology, the GON including an NNR model parameter set unit, an NNR layer parameter set unit, an NNR topology unit, an NNR quantization unit, and an NNR compressed data unit; and reconstructing the independent neural network with the topology by decoding the GON.

Co-clustering of at least some parameters is employed to reduce data transferred between edge and cloud resources. Single-parameter cluster information, including cluster counts, for each of two or more parameters of interest is accessed. Each parameter may represent a time series of numeric values sent from an IoT unit to an edge device. A co-clustering ratio is determined for each unique parameter pair. The co-clustering ratio indicates whether the number of clusters produced by a co-clustering algorithm applied to a group of parameters is less than the number of clusters required to represent the parameters without co-clustering. Co-cluster groups may be identified based on the cluster ratios. For each co-cluster group, the co-clustering algorithm may be invoked to produce compressed encodings of numeric value tuples. The compressed encoding is then transmitted to a cloud computing resource and decoded into a tuple of surrogate values.

Operational n-state digital circuits and n-state switching operations with n and integer greater than 2 execute Finite Lab-transformed (FLT) n-state switching functions to process n-state signals provided on at least 2 inputs to generate an n-state signal on an output. The FLT is an enhancement of a computer architecture. Cryptographic apparatus and methods apply circuits that are characterized by FLT-ed addition and/or multiplication over finite field GF(n) or by addition and/or multiplication modulo-n that are modified in accordance with reversible n-state inverters, and are no longer known operations. Cryptographic methods processed on FLT modified machine instructions include encryption/decryption, public key generation, and digital signature methods including Post-Quantum methods. They include modification of isogeny based, NTRU based and McEliece based cryptographic machines.

Operational n-state digital circuits and n-state switching operations with n and integer greater than 2 execute Finite Lab-transformed (FLT) n-state switching functions to process n-state signals provided on at least 2 inputs to generate an n-state signal on an output. The FLT is an enhancement of a computer architecture. Cryptographic apparatus and methods apply circuits that are characterized by FLT-ed addition and/or multiplication over finite field GF(n) or by addition and/or multiplication modulo-n that are modified in accordance with reversible n-state inverters, and are no longer known operations. Cryptographic methods processed on FLT modified machine instructions include encryption/decryption, public key generation, and digital signature methods including Post-Quantum methods. They include modification of isogeny based, NTRU based and McEliece based cryptographic machines.

A disclosed information handling system includes an edge device communicatively coupled to a cloud computing resource. The edge device is configured to respond to receiving, from an internet of things (IoT) unit, a numeric value for a parameter of interest by determining a compressed encoding for the numeric value in accordance with a non-lossless compression algorithm. The edge device transmits the compressed encoding of the numeric value to the cloud computing resource. The cloud computing resource includes a decoder communicatively coupled to the encoder and configured to respond to receiving the compressed encoding by generating a surrogate for the numeric value. The surrogate may be generated in accordance with a probability distribution applicable to the parameter of interest. The compression algorithm may be a clustering algorithm such as a k-means clustering algorithm.