A parallel-to-serial interface circuit includes an equalizer to delay odd data by a half period and sequentially generate odd pre data, odd main data, and odd post data, and delay even data by a half period and sequentially generate even pre data, even main data, and even post data, a final parallel-to-serial converter to sequentially and alternately select the even pre data and the odd pre data to generate pre data, sequentially and alternately select inverted odd main data and inverted even main data to generate inverted main data, and sequentially and alternately select the even post data and the odd post data to generate post data, and a driver to drive the pre data to generate a pre data level, drive the inverted main data to generate an inverted main data level, and drive the post data to generate a post data level.

A parallel-to-serial interface circuit includes an equalizer to delay odd data by a half period and sequentially generate odd pre data, odd main data, and odd post data, and delay even data by a half period and sequentially generate even pre data, even main data, and even post data, a final parallel-to-serial converter to sequentially and alternately select the even pre data and the odd pre data to generate pre data, sequentially and alternately select inverted odd main data and inverted even main data to generate inverted main data, and sequentially and alternately select the even post data and the odd post data to generate post data, and a driver to drive the pre data to generate a pre data level, drive the inverted main data to generate an inverted main data level, and drive the post data to generate a post data level.

A cable assembly has a cable with a transceiver module on one end. The transceiver module is plugged into an interface connector of a circuit card, which also has a network interface controller chip, an onboard non-volatile memory, and a control unit. The control unit reads cable assembly data stored in a non-volatile memory of the transceiver module over a serial bus and copies the cable assembly data to the onboard non-volatile memory. The control unit initiates transfer of the cable assembly data from the onboard non-volatile memory to a communication port of the network interface controller chip over another serial bus.

A semiconductor device includes: a data sampler configured to receive a data signal having a first frequency and to sample the data signal with a clock signal having a second frequency, higher than the first frequency, to output data for a time corresponding to a unit interval of the data signal; an error sampler configured to sample the data signal with an error clock signal having the second frequency and a phase, different from a phase of the clock signal, to output a plurality of pieces of error data for the time corresponding to the unit interval; and an eye-opening monitor (EOM) circuit configured to compare the data with each of the plurality of pieces of error data to obtain an eye diagram of the data signal in the unit interval.

A serializer includes: an I2C controller, an I2C command analysis circuit, a system control circuit, a low-speed data transmission circuit, a high-speed data conversion circuit, a low-speed data processing circuit, a parallel-serial conversion bidirectional circuit, a serial-parallel conversion circuit, a protocol analysis circuit, a video data processing circuit and an I2C receiver. The serializer can receive the external control command from the external controller through the I2C controller, and can also receive the external control command and the internal control command through the parallel-serial conversion bidirectional circuit. In addition, the serializer can also receive the video data from the external video source through the serial-parallel conversion circuit, and receive the audio data from the external source through the I2C receiver. Therefore, the serializer in the present disclosure can be applied to both two application scenarios, which is more flexible in application.

A serializer includes: an I2C controller, an I2C command analysis circuit, a system control circuit, a low-speed data transmission circuit, a high-speed data conversion circuit, a low-speed data processing circuit, a parallel-serial conversion bidirectional circuit, a serial-parallel conversion circuit, a protocol analysis circuit, a video data processing circuit and an I2C receiver. The serializer can receive the external control command from the external controller through the I2C controller, and can also receive the external control command and the internal control command through the parallel-serial conversion bidirectional circuit. In addition, the serializer can also receive the video data from the external video source through the serial-parallel conversion circuit, and receive the audio data from the external source through the I2C receiver. Therefore, the serializer in the present disclosure can be applied to both two application scenarios, which is more flexible in application.

A system and method for serializing output includes shift registers that sample a deserialized input signal at a relatively slow clock speed. Data latency between the input and output signals is controllable to a higher granularity than the input signal with bit positions corresponding to the high-speed input signal. A predictive learning algorithm receives data latency values from the input signal and corresponding data latency values from the output signal to correct and control output latency, potentially within one high speed clock cycle.

A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.

This invention enables to efficiently improve the signal-to-noise power ratio of a delta-sigma modulator without increasing the operating frequency. A digital modulation device 40 includes: a setting unit 41 that sets mutually different default values for N delta-sigma modulation units 42-1 to 42-N; N delta-sigma modulation units 42-1 to 42-N that input signals for each clock cycle indicated in a first clock signal and then perform delta-sigma modulation on the input signals to output modulated signals including noise signals having values that change in accordance with default values; and a serial output unit 43 that inputs, in order, the modulated signals output by the delta-sigma modulation units 42-1 to 42-N for each clock cycle indicated in a second clock signal, the second clock signal having a clock cycle that is 1/N of the clock cycle of the first clock signal, and then serializes and outputs the modulated signals.

This invention enables to efficiently improve the signal-to-noise power ratio of a delta-sigma modulator without increasing the operating frequency. A digital modulation device 40 includes: a setting unit 41 that sets mutually different default values for N delta-sigma modulation units 42-1 to 42-N; N delta-sigma modulation units 42-1 to 42-N that input signals for each clock cycle indicated in a first clock signal and then perform delta-sigma modulation on the input signals to output modulated signals including noise signals having values that change in accordance with default values; and a serial output unit 43 that inputs, in order, the modulated signals output by the delta-sigma modulation units 42-1 to 42-N for each clock cycle indicated in a second clock signal, the second clock signal having a clock cycle that is 1/N of the clock cycle of the first clock signal, and then serializes and outputs the modulated signals.