Systems and methods for reducing jitter due to power supply noise in an integrated circuit by drawing additional current. The additional current causes the total current to generally have a frequency higher than a resonant frequency of the integrated circuit and/or a power distribution network of the integrated circuit. A power distribution network may supply power to components of an integrated circuit, and data driver circuitry may draw first current to drive a serial data signal generated from a parallel data signal. Compensation circuitry may receive the parallel data signal and draw second current at times when the compensation circuitry determines data driver circuitry is not drawing the first current based on the parallel data signal, thereby causing a net of the first and second current to be higher than a resonant frequency range of the integrated circuit device and/or a component of the integrated circuit device.

Systems and methods for reducing jitter due to power supply noise in an integrated circuit by drawing additional current. The additional current causes the total current to generally have a frequency higher than a resonant frequency of the integrated circuit and/or a power distribution network of the integrated circuit. A power distribution network may supply power to components of an integrated circuit, and data driver circuitry may draw first current to drive a serial data signal generated from a parallel data signal. Compensation circuitry may receive the parallel data signal and draw second current at times when the compensation circuitry determines data driver circuitry is not drawing the first current based on the parallel data signal, thereby causing a net of the first and second current to be higher than a resonant frequency range of the integrated circuit device and/or a component of the integrated circuit device.

A parallel-serial conversion circuit including a data transmission unit to output first data and second data of a prescribed pattern in accordance with a second clock obtained by dividing a first clock, a first flip flop to receive the first data so as to output the first data in accordance with the first clock, a second flip flop to receive the second data so as to output the second data in accordance with the first clock, a selector to select one of the first data and the second data so as to output the selected data in accordance with the first clock, and an adjustment unit to compare the second data to be received by the second flip flop and the first data output from the first flip flop so as to adjust, based on a comparison result, a timing for the first flip flop to receive the first data.

A parallel-serial conversion circuit including a data transmission unit to output first data and second data of a prescribed pattern in accordance with a second clock obtained by dividing a first clock, a first flip flop to receive the first data so as to output the first data in accordance with the first clock, a second flip flop to receive the second data so as to output the second data in accordance with the first clock, a selector to select one of the first data and the second data so as to output the selected data in accordance with the first clock, and an adjustment unit to compare the second data to be received by the second flip flop and the first data output from the first flip flop so as to adjust, based on a comparison result, a timing for the first flip flop to receive the first data.

A clock generation circuit may be provided. The clock generation circuit may include a master DLL (Delay Locked Loop) circuit, a code divider and a slave DLL circuit. The master DLL may generate a phase pulse signal having a pulse width corresponding to one cycle of a clock signal, and may generate a delay control code corresponding to the phase pulse signal. The code divider may generate a divided delay control code corresponding to a predetermined time by dividing the delay control code. The slave DLL circuit may generate a delayed strobe signal by delaying a strobe signal according to the divided delay control code.

A clock generation circuit may be provided. The clock generation circuit may include a master DLL (Delay Locked Loop) circuit, a code divider and a slave DLL circuit. The master DLL may generate a phase pulse signal having a pulse width corresponding to one cycle of a clock signal, and may generate a delay control code corresponding to the phase pulse signal. The code divider may generate a divided delay control code corresponding to a predetermined time by dividing the delay control code. The slave DLL circuit may generate a delayed strobe signal by delaying a strobe signal according to the divided delay control code.

Circuit and method for encoding an analog signal to a stream of bits at an Analog to Digital Converter (ADC) and subsequent reconstruction of the original signal from the bit stream at a Digital to Analog Converter (DAC), where the ADC module samples the analog signal at a sub-Nyquist rate and encodes the samples to a stream of bits. The bit steam is subsequently used to reconstruct the Nyquist-rate samples of the original analog signal at the DAC. The ADC samples the input signal in one of the two realizations of non-uniform sampling, namely, Random Sampling (RS) and Level Crossing (LC) sampling techniques, according to embodiments of the disclosed invention.

An integrated circuit (IC) includes a serial-to-parallel converter configured to receive a serial input signal to provide one or more parallel output signals. The serial input signal is an M-level Pulse-Amplitude Modulated (PAM) signal, wherein M is a positive integer. The serial-to-parallel converter includes a data converter configured to receive the serial input signal and provide a data converter output signal. The data converter output signal represents information of the serial input signal with N1 bits, and N1 is a positive integer. An encoder is configured to encode the data converter output signal to provide encoder output signal with N2 bits, wherein N2 is a positive integer less than half of N1. One or more sub-deserializers are configured to receive the encoder output signal and generate the one or more parallel output signals.

An integrated circuit (IC) includes a serial-to-parallel converter configured to receive a serial input signal to provide one or more parallel output signals. The serial input signal is an M-level Pulse-Amplitude Modulated (PAM) signal, wherein M is a positive integer. The serial-to-parallel converter includes a data converter configured to receive the serial input signal and provide a data converter output signal. The data converter output signal represents information of the serial input signal with N1 bits, and N1 is a positive integer. An encoder is configured to encode the data converter output signal to provide encoder output signal with N2 bits, wherein N2 is a positive integer less than half of N1. One or more sub-deserializers are configured to receive the encoder output signal and generate the one or more parallel output signals.

The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.