An apparatus is described. The apparatus includes a memory chip. The memory chip has an error correction code (ECC) encoder logic circuit and an ECC decoder logic circuit. The ECC decoder logic circuit is to place an additional one or more errors that result from incorrect error correction applied to a read code word into a same block of multiple blocks of the read code word's raw data bit portion where original errors in the read code word existed before the read code word was decoded by the ECC decoder logic circuit.

Systems, apparatuses, and methods for training procedures on reference voltages and sampling times associated with symbols communicated with a memory device are described. The training procedures may be configured to compensate for variations that may occur in different symbols of a signal. For example, an individual training operation may be performed for each reference voltage within a first unit interval. These individual training operations may allow a reference voltage of the first unit interval to be positionable independent of other reference voltages in the same unit interval or in different unit intervals. In another example, an individual training operation may be performed for the sampling time associated with a reference voltage. These individual training operations may allow a sampling time associated with a reference voltage in the first unit interval to be positionable independent of other sampling times in the same unit interval or in different unit intervals.

The present disclosure relates to the field of communication technologies, and discloses a polar coding/decoding method and apparatus, to improve sequence lookup efficiency. The method includes: obtaining a first sequence from a polar code construction sequence table based on a coding parameter, where the polar code construction sequence table includes at least one coding parameter and at least one sequence corresponding to the at least one coding parameter, the at least one coding parameter is mapped to the at least one sequence in a one-to-one manner, the first sequence is one of the at least one sequence; selecting serial numbers of K polarized channels from the first sequence based on a rate matching scheme and/or a reliability order; placing to-be-coded bits based on the selected serial numbers of the K polarized channels; and performing polar coding, to obtain a coded bit sequence.

Disclosed are systems, methods, and software for generating spatially-coupled low-density parity-check (SC-LDPC) codes. A method for generating SC-LDPC codes includes generating one or more quasi-cyclic low-density parity-check (QC-LDPC) codes, and also includes assigning at least one of the generated one or more QC-LDPC codes as one or more template codes. The method further includes copying at least a portion of the one or more template codes to introduce irregularity. The method also includes shifting one or more template codes on a sub-block basis to generate at least one SC-LDPC code. As compared to known LDPC code generation modalities, the disclosed invention provides a simplified technique for implementation in streamlined hardware which has more general applicability across both present, and anticipated, communication systems, including those adapted for use with optical communications, wireless communications, and 5G as well as future 6G.

A bit interleaving method involves applying a bit permutation process to a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N/M folding sections, each of the constellation words being associated with one of the F×N/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word

A bit interleaving method involves applying a bit permutation process to a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N/M folding sections, each of the constellation words being associated with one of the F×N/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.

A system for transmitting information may include a server that generates pseudo-random superpositions, each superposition including multiple packet fragments encoded using a Galois field. The system may transmit the superpositions across a plurality of communication links, which form a single logical path, to a client device. Communication links may include a combination of diverse communication channels, and more preferably one or more low latency (but low bandwidth) communication links and one or more high bandwidth (but high latency) communication links. Advantageously, the use of a plurality of communication links may facilitate transmitting information quickly and reliably.

A RAID storage-device-assisted parity data update system includes a first RAID primary data drive that DMA's second primary data from a host system, and XOR's it with first primary data to produce first interim parity data for a first data stripe. A second RAID primary data drive DMA's fourth primary data from the host system, and XOR's it with third primary data to produce second interim parity data for a second data stripe. A first RAID parity data drive DMAs the first interim parity data and XOR's it with first parity data to produce second parity data for the first data stripe that overwrites the first parity data. A second RAID parity data drive DMA's the second interim parity data and XOR's it with third parity data to produce fourth parity data for the second data stripe that overwrites the third parity data.

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver is formed of a plurality of columns each including a plurality of rows and includes a block interleaver configured to divide each of the plurality of columns into a first part and a second part and interleave the LDPC codeword, the number of rows constituting each column divided into the first part is determined differently depending upon the modulation method, wherein the number of rows constituting each column divided into the second part is determined depending upon the number of rows constituting each column divided into the first part.