A method includes writing sets of encoded data slices to storage units of a storage network in accordance with error encoding parameters, where for a set of encoded data slices, the error encoding parameters include an error coding number and a decode threshold number, the error coding number indicates a number of encoded data slices that results when a data segment is encoded using an error encoding function and the decode threshold number indicates a minimum number needed to recover the data segment. The method further includes monitoring processing of the writing the sets of encoded data slices to produce write processing performance information. When the write processing performance information compares unfavorably to a desired write performance range, the method further includes adjusting at least one of the error coding number and the decode threshold number to produce adjusted error encoding parameters for writing subsequent encoded data slices.

Error correction procedures for a memory device including a memory die having an array of memory cells including a plurality of banks are described. The memory die includes a first error correcting code (ECC) circuit coupled with a first bank of memory cells, where the first ECC circuit is configured to perform operations associated with a first access operation (e.g., write operation) of the first bank of memory cells. The memory die further includes a second ECC circuit coupled with the first bank of memory cells, where the second ECC circuit is configured to perform ECC operations associated with a second access operation (e.g., read operation) of the first bank. In some cases, the first ECC circuit is located under the footprint of the array and the second ECC circuit is located outside the footprint of the array.

For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

Methods and apparatus are provided for controlling wireless signal transmissions, wherein problematic symbol patterns are relocated to an erasure region of a data packet prior to erasure encoding and transmission. Relocating the problematic symbol patterns is done so that, when the resulting erasure codeword is punctured and transmitted, the problematic patterns are not transmitted. Yet, those patterns can be restored by the decoder at the receiving device using an erasure decoder in accordance with erasure decoding techniques, e.g., punctured low-density parity-check (LDPC) decoding techniques. In this manner, problematic symbol patterns that may be corrupting during transmission due to noise are removed (punctured) prior to transmission, then restored by the decoder during decoding.

Disclosed is a network-based hyperdimensional system having an encoder configured to receive input data and encode the input data using hyperdimensional computing to generate a hypervector having encoded data bits that represent the input data. The network-based hyperdimensional system further includes a decoder configured to receive the encoded data bits, decode the encoded data bits, and reconstruct the input data from the decoded data bits. In some embodiments, the encoder is configured for direct hyperdimensional learning on transmitted data with no need for data decoding by the decoder.

Disclosed are a method and apparatus for generating a decoding position control signal for decoding using polar codes. The method and apparatus for generating a decoding position control signal for decoding using polar codes according to an embodiment of the present disclosure include generating a decoding tree obtained by forming a plurality of nodes in a hierarchical structure for a polar-encoded codeword, decoding the codeword using a successive cancellation (SC) decoding technique, and generating control signal through a preset operation relationship based on a position of a bit returned during re-decoding among the decoded codeword.

A memory system includes an encoder and a decoder. The encoder is configured to generate multi-dimensionally-coded data to be written into the non-volatile memory. Data bits of the multi-dimensionally-coded data are grouped into first and second dimensional codes with respect to first and second dimensions, respectively. The decoder is configured to, with respect to each of the first and second dimensional codes included in read multi-dimensionally-coded data, generate a syndrome value of the dimensional code, generate low-reliability location information, generate a soft-input value based on the syndrome value and the low-reliability location information, decode the dimensional code through correction of the dimensional code using the soft-input value, and store modification information indicating a bit of the dimensional code corrected through the correction and reliability information indicating reliability of the correction. The decoder generates the soft-input value also based on the modification information and the reliability information in the memory.

Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.

A CRC code is generated from an original data, a BCH code is generated with respect to the original data and the CRC code, and the original data, the CRC code, and the BCH code are recorded in pages selected from different planes of a plurality of memory chips. An RS code is generated from the original data across pages, a CRC code is generated with respect to the RS code, a BCH code is generated with respect to the RS code and the CRC code, and the RS code, the CRC code, the BCH code are recorded in a memory chip different from a memory chip including the original data. When reading data, error correction is performed on the original data by using the BCH code, and then CRC is calculated. If the number of errors is the number of errors that is correctable by erasure correction using the RS code, the original data is corrected by the erasure correction. If the number of errors exceeds an erasure correction capability of the RS code, normal error correction using the RS code is performed, and further error correction using the BCH code is performed.

A method includes calculating a number of iterative detection and decoding (IDD) iterations and a number of decoding iterations for each of a plurality of channel coding units in a target codeword; calculating a demodulation time and a decoding time for the target codeword based on the number of IDD iterations and the number of decoding iterations for the target codeword; adding the target codeword to a codeword set, based on a demodulation time and a decoding time for codewords in the codeword set and the target codeword; and performing an IDD operation based on a number of IDD iterations and a number of decoding iterations.