There are provided methods and systems for on-ASIC error control coding for verifying the integrity of data from a memory. For example, there is provided a method for encoding data into a beat. The method can be executed by a digital system configured to receive the data and construct the beat. The method includes assembling, by the digital system, a plurality of words consecutively. The plurality of words can include a first set of words in which each word has a length W, where W is the beat width. The plurality of words can further include a second set of words in which each word has a length that is smaller or equal to W. The method can further include constructing a parity word of length W, wherein each bit in the parity word is a parity associated with a distinct word in the first and second set of words. The method further includes adding the parity word to the plurality of words to form the beat.

Methods, systems, and devices for syndrome check functionality to differentiate between error types are described. A host system, a memory system, or some combination of both may include syndrome check circuitry to provide enhanced error diagnostic capabilities for data communicated between the host system and the memory system. The syndrome check circuitry may receive a first signal from the memory system indicating whether the memory system detected and attempted to correct an error in the data and may receive a second signal from the host system indicating whether the host system detected an error in the received data. The syndrome check circuitry may compare the first signal and the second signal using a set of logic gates to differentiate between different combinations of errors detected at one or both of the memory system or the host system.

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.

A method for differentiator-based compression of digital data includes (a) multiplying a tap-weight vector by an original data vector to generate a predicted signal, the original data vector comprising N sequential samples of an original signal, N being an integer greater than or equal to one, (b) using a subtraction module, subtracting the predicted signal from a sample of the original signal to obtain an error signal, (c) using a quantization module, quantizing the error signal to obtain a quantized error signal, and (d) updating the tap-weight vector according to changing statistical properties of the original signal.

A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to generate a plurality of bit groups each of which is formed of a same number of bits, determine whether a number of the outer-encoded bits satisfies a predetermined number of bits required according to at least one of a code rate and a code length for Low Density Parity Check (LDPC) encoding, pads zero bits to some of the bits in the bit groups if the number of the outer-encoded bits is less than the predetermined number of bits, and maps the outer-encoded bits to remaining bits in the bit groups, based on a predetermined shortening pattern, thereby to constitute LDPC information bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the some of the bits, in which zero bits are padded, are included in some of the bit groups which are not sequentially disposed in the LDPC information bits.

A method for execution by a storage network begins by issuing a decode threshold number of read requests for a set of encoded data slices to a plurality of storage units of a set of storage units and continues by determining whether less than a decode threshold number of read requests has been received in a time window. The method continues by identifying one or more encoded data slices encoded data slices associated with read requests of the decode threshold number of read requests that have not been received and for an encoded data slice of the one or more encoded data slices, issuing a priority read request to a storage unit storing a copy of the encoded data slice. The method then continues by receiving a response from the storage unit storing the copy of the encoded data, where the storage unit storing the copy of the encoded data slice is adapted to delay one or more maintenance tasks in response to the priority read request.

A three-dimensional data encoding method includes: generating an N-ary tree structure of three-dimensional points included in three-dimensional data, where N is an integer greater than or equal to 2; generating first encoded data by encoding a first branch using a first encoding process, the first branch having, as a root, a first node included in a first layer that is one of layers included in the N-ary tree structure; generating second encoded data by encoding a second branch using a second encoding process different from the first encoding process, the second branch having, as a root, a second node included in the first layer and different from the first node; and generating a bitstream including the first encoded data and the second encoded data.

Embodiments are directed to collision-free hashing for accessing cryptographic computing metadata and for cache expansion. An embodiment of an apparatus includes one or more processors to: receive a physical address; compute a set of hash functions using a set of different indexes corresponding to the set of hash functions, wherein the set of hash functions combine additions, bit-level reordering, bit-linear mixing, and wide substitutions, wherein the plurality of hash functions differ in the bit-linear mixing; access a plurality of cache units utilizing the set of hash functions; read different sets of the plurality of cache units in parallel, where a set of the different sets is obtained from each cache unit of the plurality of cache units; and responsive to the physical address being located one of the different sets, return cache line data of the set corresponding to the set of the cache unit having the physical address.

A first communication device and a second communication device for an iterative code design are provided. The first communication device generates and transmits sets of parity symbols and receives the transmitted sets of parity symbols from a second communication device. The sets of parity symbols are generated based on using a first generator device and based previously transmitted systematic symbols and computed noise values. The second communication device buffers received systematic symbols and sets of parity symbols and jointly decodes them. Thereby, an iterative code design is provided with improved performance. Furthermore, the disclosure also relates to corresponding methods and a computer program.

Systems, methods, and instrumentalities are described herein that may be used for reduced complexity polar encoding and decoding. There may be a set of encoding nodes to be used for polar encoding. An encoding node may be associated with a bit index and/or a relaxation level. A relaxation attribute may be selected for the encoding node. A relaxation group may be determined based on the relaxation attributes. The relaxation group may include two encoding nodes associated with consecutive bit indexes, an initial relaxation level, and the first relaxation attribute. A final relaxation level may be determined. Relaxation may be performed on the encoding nodes in the relaxation group. For example, an XOR operation between the encoding nodes may be omitted. Relaxation may be performed on the encoding nodes associated with each relaxation level up to the final relaxation level.