A system for transmission of quantum information for quantum error correction includes an ancilla qubit chip including a plurality of ancilla qubits, and a data qubit chip spaced apart from the ancilla qubit chip, the data qubit chip including a plurality of data qubits. The system includes an interposer coupled to the ancilla qubit chip and the data qubit chip, the interposer including a dielectric material and a plurality of superconducting structures formed in the dielectric material. The superconducting structures enable transmission of quantum information between the plurality of data qubits on the data qubit chip and the plurality of ancilla qubits on the ancilla qubit chip via virtual photons for quantum error correction.

The technology disclosed herein pertains to a system for data integrity verification that is optimized at unit level. One or more implementations of such system include a method including identifying a first unit boundary in data block received from a client at an application layer, the unit boundary indicating end of a first unit of data, generating an intermediate checksum for the first unit of data at the application layer, receiving a second unit of data of the data block at the application layer, and generating a final checksum with an intermediate checksum as a basis and the second unit of data.

The present application discloses a Hamming weight calculation method performed by an operation apparatus. The operation apparatus includes a controller and a first calculator, wherein the controller sets an initial resistance state of the first memory to a low resistance state; determines a first gate voltage of the first transistor based on first bit data in a first binary sequence, and control an on-off state of the first transistor based on the first gate voltage; controls a target resistance state of the first memory based on the on-off state of the first transistor; and determines a Hamming weight of the first bit data based on a first output current on the source of the first transistor.

A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If “A” is higher than 10, the code generation matrix is generated when (A−10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least one of an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of a minimum Hamming distance.

Certain aspects of the present disclosure generally relate to wireless communications and, more particularly, to methods and apparatus for rate-matching control channels using polar codes. An exemplary method generally includes encoding a stream of bits using a polar code, determining a size of a circular buffer for storing the encoded stream of bits based, at least in part, on a minimum supported code rate and a control information size, and performing rate-matching on stored encoded stream of bits based, at least in part, on a mother code size, N, and a number of coded bits for transmission, E.

Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.

The present technology relates to a transmission method and a reception device for securing favorable communication quality in data transmission using an LDPC code. In group-wise interleaving, the LDPC code with a code length N of 17280 bits is interleaved in units of 360-bit bit groups 0 to 47. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence. The present technology can be applied, for example, in a case of performing data transmission using an LDPC code, and the like.

This disclosure provides a data retransmission method and apparatus. The method includes: A transmitting device obtains information to be transmitted for a t.sup.th time, where the information to be transmitted for the t.sup.th time includes R.sub.t extension locations and information to be transmitted for a (t−1).sup.th time, and the extension locations include M.sub.t information bits and L.sub.t check bits corresponding to the M.sub.t information bits. The transmitting device then performs Polar encoding on the information to be transmitted for the t.sup.th time, to obtain a codeword after the Polar encoding, obtains a codeword for (t−1).sup.th retransmission based on the codeword after the Polar encoding, and transmits the codeword for (t−1).sup.th retransmission. A receiving device performs polar decoding after receiving the codeword for (t−1).sup.th retransmission, to obtain a decoding result of codewords for t times of transmission. By performing, on an encoding side, check encoding on the information bits in an extension part, a decoding path can be reduced in a decoding process, thereby greatly reducing decoding complexity, and reducing storage overheads and calculation overheads.

A hardware architecture for systematic erasure encoding includes first matrix constructor circuit that receives parity-check matrix H for codeword C, and the erased part of codeword C, and outputs matrix H.sub.1 of columns of H located on erased coordinates of code C; second matrix constructor circuit that receives matrix H and the erased part of codeword C and outputs matrix H.sub.2 of columns of H located on non-erased coordinates of code C; a neural network that calculates matrix J.sub.1 that is an approximate inverse of matrix H.sub.1. The matrix J.sub.1 is used to determine new erasures in the parity matrix H and new erased coordinates. Matrices H.sub.1 and H.sub.2 are updated, and the updated H.sub.1 is provided as feedback to the first matrix constructor circuit. A calculator circuit restores the erased coordinates of codeword C, from the matrix J.sub.1, matrix H.sub.2, and a non-erased part of codeword C.

A zero padding apparatus and method for fixed length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.