A high-speed serial interface (HSIF) for communicating between an analog front end (AFE) and a radio via a bi-directional serial bit connection for an OFDM device.

Methods, apparatus, and systems for communication over a multi-wire, multi-phase interface are disclosed. A clock recovery method includes generating a combination signal that includes transition pulses, each transition pulse being generated responsive to a transition in a difference signal representative of a difference in signaling state of a pair of wires in a three-wire bus. The combination signal is provided to a logic circuit that is configured to provide a clock signal as its output, where pulses in the combination signal cause the clock signal to be driven to a first state. The logic circuit receives a reset signal that is derived from the clock signal by delaying transitions to the first state while passing transitions from the first state without added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state.

A method for operating a wireline communication device on a wireless communication network includes (a) receiving a downlink radio frequency (RF) electrical signal at a first connector, (b) converting the downlink RF electrical signal to a downlink access signal having a format that is compatible with the wireline communication device, and (c) providing the downlink access signal to a second connector for transporting to the wireline communication device. A method for extending a wireline communication network includes (a) receiving a downlink wireline signal at a node of the wireline communication network, (b) converting the downlink wireline signal to a downlink RF electrical signal, and (c) converting the downlink RF electrical signal to a downlink wireless signal, for transmission to one or more communication devices which are not physically connected to the wireline communication network.

A signal-to-noise and interference ratio (SNAIR) aware analog to digital converter (ADC)-based receiver and a method thereof is disclosed. The SNAIR aware-ADC based receiver comprises an analog front end (AFE) configured for recovering an input data signal with a bit error rate (BER) below a target BER. The SNAIR aware-ADC based receiver further comprises a sampler communicatively coupled to the AFE. A DSP unit is communicatively coupled to the SADC array. The DSP unit comprises a feed forward equalizer (FFE) configured to remove residual inter-symbol interference (ISI) by multiplying a delayed version of the digital data signal with Htap values. The CDR system is configured to process the generated plurality of error signals and data signals. An eye quality measurement system is communicatively coupled to an output of the DSP unit. A digital control communicatively coupled to each of the AFE, the sampler, the SADC array, the DSP unit, and the eye quality measurement system.

A wideband buffer circuit and a wideband communication circuit that uses the wideband buffer circuit. The wideband buffer circuit includes first and second transistors deployed as a voltage buffer and connected to first and second input terminals, first and second parallel resistor-capacitor pairs connected to the first and second transistors, first and second cross-coupled transistors connected to the first and second parallel resistor-capacitor pairs and connected to first and second output terminals, and first and second current sources connected to the first and second cross-coupled transistors and a fixed voltage. The first transistor, the first parallel resistor-capacitor pair, the first cross-coupled transistor and the first current source are connected in series. The second transistor, the second parallel resistor-capacitor pair, the second cross-coupled transistor and the second current source are connected in series.

Aspects of the subject disclosure may include a generator that facilitates generation of an electromagnetic wave, a core, and a waveguide that facilitates guiding the electromagnetic wave towards the core to induce a second electromagnetic wave that propagates along the core. The core and/or the waveguide can be configured to reduce radiation loss of the second electromagnetic wave, propagation loss of the second electromagnetic wave, or a combination thereof. Other embodiments are disclosed.

A sensor 1 is arranged to read data transmitted on a digital vehicle network. The sensor comprises a wire holding unit 3, and a sensing unit 5. The wire holding unit and sensing unit are connectable to one another, the sensor further comprising a locking mechanism to lock the wire holding unit and the sensing unit together, when the wire holding unit and sensing unit are connected to one another.

A high-speed serial interface (HSIF) for communicating between an analog front end (AFE) and a System on a Chip (SoC) digital radio via a bi-directional serial bit connection for an OFDM cable modem includes generating Status Frames and Data Frames to be communicated between the tuner and AFE and sending the generated Status Frames and Data Frames on a continual basis. Each Frame is a 10-bit K.28 Comma Sync word followed by a payload and when no data is queued to be communicated, Status Frames are sent asynchronously as filler frames.

An audio signal processing method of an audio signal distribution device including a receiver, a determiner, and a transmitter. The receiver receives information relating to capabilities of a distribution destination device to which an audio signal is distributed. The determiner, based on the capabilities of the distribution destination device in received information, determines a role of processing of the audio signal of each device including an own device and the distribution destination device and generates processing information according to the processing of the audio signal. The transmitter distributes the processing information and the audio signal to the distribution destination device.

An apparatus for generating a substantially constant DC reference voltage. The apparatus includes a reference voltage generator configured to generate a substantially constant direct current (DC) reference voltage based on a voltage on a data signal transmission line, wherein the voltage is based on a bandgap reference voltage. In one implementation, the data signal transmission line is a differential signal transmission line and the voltage is a common mode voltage. In another implementation, the data signal transmission line is an I-data signal transmission line and a Q-data signal transmission line, and the voltage is an average or weighted-average of the common mode voltages of the I- and Q-differential signals. In another implementation, the reference voltage is based on a single-ended (e.g., positive- and/or negative)-component or vice-versa of I- and Q-data signals, respectively.