Disclosed is a card clock recovery system for use in an NFC card transceiver couplable to an NFC reader. The card clock recovery system has: a phase lock loop having: a phase/frequency detector, which is configured to receive a reference signal provided at an RX port of a matching network during a receiving mode of the NFC transceiver or to receive a reference signal provided at the RX port of the matching network during a transmission mode of the NFC transceiver, to receive a loop feedback signal, and to provide a phase error signal that represents a phase difference between the reference signal and the loop feedback signal; a loop filter configured to receive a corrected phase error signal that is derived from the phase error signal, and to provide a filtered corrected phase error signal; a controllable oscillator, which is configured to receive the filtered corrected phase error signal and to provide a controlled frequency output signal, which is provided as the card clock generation control signal to a card clock generation unit of an NFC card transceiver, and as the loop feedback signal, via the loop feedback line, to the phase/frequency detector. The card clock recovery system further has a phase offset correction unit, which is configured to receive the phase error signal provided by the phase/frequency detector and to provide the corrected phase error signal to the loop filter, and which has a phase error sampling unit, a phase offset computation unit, and a phase subtractor unit.

One example includes an isochronous receiver system. The system includes a pulse receiver configured to receive an input data signal from a transmission line and to convert the input data signal to a pulse signal. The system also includes a converter system comprising a phase converter system. The phase converter system includes a plurality of pulse converters associated with a respective plurality of sampling windows across a period of an AC clock signal. At least two of the sampling windows overlap at any given phase of the AC clock signal, such that the converter system is configured to generate an output pulse signal that is phase-aligned with at least one of a plurality of sampling phases of the AC clock signal based on associating the pulse signal with at least two of the sampling windows.

A base station and the customer premises equipment (CPE) transceivers are configured to use a single master clock for all frequency conversions. The modem of each CPE has a clock output and that output is connected to the upconverter in the transceiver uplink or to both the upconverter and the downconverter as required.

A communication device includes an interleaving unit that determines an interleaving length of transmit data to be transmitted through free-space optical communication, and interleaves the transmit data based on the determined interleaving length, and a shaping unit that shapes the interleaved transmit data so as to make the interleaving length detectable on a receiving side of the free-space optical communication.

A method of estimating a clock frequency offset in a mobile device relative to a clock frequency of a controller within a UWB network comprises (a) determining, for each of a plurality of anchors, an anchor clock frequency offset relative to the controller clock frequency, (b) broadcasting an anchor data packet from each anchor, the anchor data packet including the respective anchor clock frequency offset, (c) receiving at least one anchor data packet at the mobile device, (d) estimating a mobile device clock frequency offset relative to the anchor clock frequency of the anchor from which the at least one anchor data packet was received, and (e) estimating the clock frequency offset in the mobile device based on the estimated mobile device clock frequency offset and the anchor clock frequency offset included in the at least one received anchor data packet. Furthermore, a TDoA-based localization method and a TDoA-based localization system are described.

The embodiment of the present disclosure provides a time code synchronization method, which includes following steps of: determining a target master node and one or more target slave nodes of a network system among the plurality of nodes; periodically sending a data packet to the one or more target slave nodes by the target master node, wherein the data packet includes a first time code and serial number information of the target master node; compensating the first time code according to the serial number information to obtain a second time code, and synchronizing the second time code by the one or more target slave nodes.

A system for synchronizing a local audio processing clock rate of a digital signal processor (DSP) to an audio clock rate of a network to which the DSP is connected. The system includes an adjustable clock synthesizer that is configured to establish the local audio processing clock rate of the DSP. The DSP is configured to generate events that are associated with the local audio processing clock rate of the DSP. The DSP is further configured to monitor the generated events over time and based on the monitored events cause the adjustable clock synthesizer to adjust the local audio processing clock rate of the DSP to better match the network audio clock rate.

A PAM-4 receiver with jitter compensation clock and data recovery is provided. The receiver includes a first-order delay-locked loop (DLL) which employs a bang-bang phase detector (BBPD) and a voltage-controlled delay line (VCDL) circuit supporting 40 MHz jitter tracking bandwidth and static phase skew elimination. A second-order wideband phase-locked loop (WBPLL) using the ¼-rate reference clock provides multi-phase clock generation with low input-to-output latency. To suppress the consequent jitter transfer, a jitter compensation circuit (JCC) acquires the jitter transfer amplitude and frequency information by detecting the DLL loop filter voltage (VLF(s)) signal, and generates an inverted loop filter voltage signal, denoted as VLF.sub.INV(s). The VLF.sub.INV(S) modulates a group of complementary VCDLs (C-VCDLs) to attenuate the jitter transfer on both recovered clock and data. With the provided receiver, a jitter compensation ratio up to 60% can be supported from DC to 4 MHz, with a −3-dB corner frequency of 40 MHz.

A method of remote communications with an on-board diagnostics (OBD) system of a vehicle includes connecting a vehicle communications device to a connector of a vehicle's OBD system, connecting a remote communications device to a connector of a vehicle tool device, and establishing a network communications link between the vehicle-communications device and a remote communications device. The vehicle communications device receives communications at the vehicle-communications device from the vehicle's OBD system through the connector. A bit stream of the received communications is analyzed over an interval of time. The widths of one or more bit pulses are estimated based on the analyzing of the bit stream. A bit rate of the OBD system is determined based on the estimated widths of the one or more bit pulses. Based on the determined bit rate of the OBD system, bidirectional communications are established between the OBD system and the tool device using the established network communications link between the vehicle-communications device and the remote communications device.

A full-duplex communication device includes an antenna, a transceiving module a conversation module and a control module. The antenna is configured to receive and send signals. Two of the transceiving module are provided, the transceiving module is installed with a filter and a gating switch connecting to the filter, operating frequencies of the two transceiving module are different, and the gating switche is configured to switch operating states between a receiving mode and a sending mode of the transceiving modules. The conversation module is connected to the transceiving modules and configured to receive and play voice signals. The control module is connected to the transceiving modules and configured to control tasks of the transceiving modules.