A memory interface may include a transmitter that generates multi-level signals made up of symbols that convey multiple bits of data. The transmitter may include a first data path for a first bit (e.g., a least significant bit (LSB)) in a symbol and a second data path for a second bit (e.g., the most significant bit (MSB)) in the symbol. Each path may include a de-emphasis or pre-emphasis buffer circuit that inverts and delays signals received at the de-emphasis or pre-emphasis buffer circuit. The delayed and inverted data signals may control de-emphasis or pre-emphasis drivers that are configured to apply de-emphasis or pre-emphasis to a multi-level signal.

A cyber security system for providing security to a railway, the system comprising: a data monitoring and processing hub; a network comprising a plurality of data collection agents synchronized to a same network clock and configured to monitor railway infrastructure devices and onboard devices of rolling stock having a train communication network (TCN), and forward monitored data to the hub for processing by the hub to detect anomalies in railway operation that are indicative of a cyber-attack; at least one anonymizer configured to scrub information items from data that the hub receives from a data collection agent of the plurality of data collection agents which may be used to identify the cyber security system or the railway for which the system provides security.

Disclosed is a method of producing an output signal from a signal generator, comprising: determining a driving input to the signal generator, the driving input for driving the signal generator to provide a predetermined output signal, wherein the output signal includes at least one frame, the at least one frame comprising an active period and a dummy period and wherein the active period and dummy period are determined by the driving input. Also disclosed is a method of producing an output signal from a signal generator, comprising: receiving a synchronisation signal; obtaining an input signal for controlling the signal generator to generate an output signal comprising at least one frame wherein the at least one frame comprises at least one active period and at least one dummy period; producing the output signal comprising a series of frames; and, synchronising the output signal with the synchronisation signal by varying a duration of the at least one of the dummy period or active period.

Synchronization of clocks among computing devices in a network includes determining master/slave relations among the computing devices. Some computing devices (e.g., switches) include trunk ports configured to carry traffic for several logical networks; e.g., virtual local area networks, VLANs. A trunk port can be associated with a master/slave setting for each logical network that it is configured for. Synchronization of clocks among the computing devices further includes running a synchronization sequence between a trunk port and each computing device on each of the logical networks configured on the trunk port.

In a hybrid network comprising both guided and wireless communications technologies, a grandmaster clock is designated in one portion of the network and can be propagated across to the other portion by means of a timing synchronization message. This message may include timestamping information and other information to enable recipient devices to correctly synchronize to the grandmaster clock.

A system includes a plurality of line cards and a timing card. A clock generation circuit on the timing card generates a clock signal which is pulse width modulated according to information to be transmitted. A clock line supplies the pulse width modulated clock signal to the line cards. The timing card sends a first control word to the plurality of line cards over the clock line after sending a beacon. The first control word includes a size field specifying a first length of first data following the first control word. The timing card sends time of day information over the clock line to the line cards following the first control word. The time of day information may be encrypted. A second control word follows the time of day information. One or more additional control words can follow the second control word before the next beacon.

A receiver converter circuit included in a computer system may receive multiple signals that encode a serial data stream that encode multiple data symbols. To correct for baseline wander, the receiver circuit may generate a disparity signal that is used to control the application of a differential voltage to the multiple signals. The receiver circuit may also employ the disparity signal to generate a gradient against which the magnitude of differential voltage is calibrated.

A time synchronization method, a time synchronization sender, a time synchronization receiver and a time synchronization system are provided. The method includes: determining whether at least one parameter causing recalculation of a best master clock (BMC) algorithm changes; in a case where it is determined that the parameter changes, sending a 1588 standard-based Announce message; and in a case where it is determined that the parameter does not change, sending a keep-alive message of the Announce message. In the present disclosure, by distinguishing keep-alive messages from protocol messages, the problem that a CPU system is busy due to the processing of Announce messages is solved, thereby realizing the optimization of the 1588 protocol, and reducing the impact on the CPU.

The present disclosure provides a method and apparatus for acquiring a timestamp of a data stream, a storage medium and an electronic apparatus. The method for acquiring the timestamp of the data stream includes: receiving a data stream to be transmitted, and acquiring a first frame header identifier of the data stream to be transmitted in a serializer-deserializer (SERDES) clock mode, the first frame header identifier being used for representing a position of a frame header of the data stream to be transmitted; determining, based on the first frame header identifier, a timestamp of the data stream to be transmitted under a system clock; encapsulating the timestamp to obtain a first target data frame; and outputting the first target data frame.

A network adapter includes a network port for communicating with a communication network, a hardware clock, and circuitry. The circuitry is coupled to receive from the communication network, via the network port, one or more time-protocol packets that convey a network time used for synchronizing network devices in the communication network, to align the hardware clock to the network time conveyed in the time-protocol packets, and to make the network time available to one or more time-service consumers running in a host served by the network adapter.