A transceiver device includes a transmitter and a receiver connected through first and second lines. A first frame period includes an active period for transmitting a first payload and a vertical blank period including a frequency hopping period. The transmitter transmits, to the first and second lines, signals having a first voltage range in a first mode and signals having a second voltage range in a second mode. The transmitter generates a first horizontal synchronization signal in the second mode except for the frequency hopping period, encodes the first horizontal synchronization signal to horizontal synchronization data, and generates a second horizontal synchronization signal in the first mode in the frequency hopping period. The transmitter adds a first clock training pattern to the horizontal synchronization data except for the frequency hopping period, and adds a second clock training pattern to first horizontal synchronization data after the frequency hopping period.

A method of reading data includes: receiving a digital signal, wherein the digital signal includes a sync signal and a data signal; performing an oversampling operation to the digital signal, and calculating a plurality of sampling points according to the oversampling operation; by a first counter counting the sampling points to obtain a first count value; based on the first count value defining a second count value; defining a unit interval; in the unit interval, defining a data reading range; and in the data reading range, reading the data signal corresponding to data of the unit interval as a first value when a potential of each of the sampling points counted is changed from a first potential to a second potential.

A method of reading data includes: receiving a digital signal, wherein the digital signal includes a sync signal and a data signal; performing an oversampling operation to the digital signal, and calculating a plurality of sampling points according to the oversampling operation; by a first counter counting the sampling points to obtain a first count value; based on the first count value defining a second count value; defining a unit interval; in the unit interval, defining a data reading range; and in the data reading range, reading the data signal corresponding to data of the unit interval as a first value when a potential of each of the sampling points counted is changed from a first potential to a second potential.

A transmission apparatus (10) according to the present disclosure incudes: a correction value calculation unit (130) configured to calculate a correction value for correcting an initial standby time of a direct wave signal or an indirect wave signal based on a reception time of the direct wave signal and a reception time of the indirect wave signal that follows the direct wave signal, and a transmission time fluctuation compensation unit (140) configured to calculate the standby time by correcting the initial standby time using the correction value and cause the direct wave signal or the indirect wave signal to stand by in accordance with the standby time. The correction value calculation unit (130) calculates a correction value for increasing the standby time of the direct wave signal or reducing the standby time of the indirect wave signal.

A semiconductor integrated circuit includes a converter converting an analog signal into a digital signal based on a clock signal; a comparator determining values of data based on the digital signal; a recovery circuit recovering the clock signal based on the digital signal and the data; and a control circuit. The recovery circuit includes a phase detector calculating a sum of a first value and offset, the first value being a value based on the digital signal and the data and relating to a phase of the clock signal; and a loop filter calculating a correction amount of the phase of the clock signal based on the sum. The control circuit is configured to gradually change the offset from a second value to zero after the second value is added as the offset.

Disclosed are systems, methods, and non-transitory computer-readable media for clock synchronization in half-duplex communication systems. Devices in a half-duplex system are synchronized based on time stamp values captured by each device that define a specified period of time that is of equal in length. The specified period of time spans two change-over periods to average the jitter and/or drift that occurs during each period. Each device uses these measured lengths to determine the variance in the rates at which the two internal clocks operates, which is then used to synchronizes the internal clocks of the two devices.

A system includes a first device and a second device coupled to a link having one or more paths associated with transmitting a clock signal. The first device is to transmit a set of bits associated with a pattern via the one more paths. The set of bits are transmitted using a first clock signal having a first frequency less than a second frequency associated with data transmission operations. The second device is to receive the set of bits associated with the pattern, determine a number of pulses associated with the set of bits over a first period, and determine the number of pulses, associated with the set of bits, satisfies a predetermined condition relating to the number of pulses for the first period. The second device is to initiate a training of the link in response to determining the number of pulses satisfies the predetermined condition.

The disclosure provides a method for correcting a 1 pulse per second (1PPS) signal and a timing receiver. In the embodiments of the disclosure, the proposed method allows the timing receiver to provide a corrected 1PPS signal with better quality to back-end slave devices, thereby ensuring that the synchronization effect of the slave devices is not overly affected by jitter in a single 1PPS signal.

A retiming circuit module, a signal transmission system and a signal transmission method are disclosed. The retiming circuit module includes a path control circuit and a multipath signal transmission circuit. The multipath signal transmission circuit includes a plurality of parallel signal transmission paths. The path control circuit is configured to control the multipath signal transmission circuit to perform signal transmission between an upstream device and a downstream device based on a first parallel signal transmission path in the parallel signal transmission paths during a period of a handshake operation performed between the upstream device and the downstream device. The path control circuit is further configured to control the multipath signal transmission circuit to perform the signal transmission based on a second parallel signal transmission path in the parallel signal transmission paths after the handshake operation is finished.

A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.