A data transfer circuit (40) according to the invention includes a memory (41) configured to write data in accordance with a write pointer in synchronization with a first clock, and read out the data in accordance with a readout pointer in synchronization with a second clock, a clock generation circuit (44) configured to generate the second clock by multiplying a reference clock by a rational number N, a frequency error estimation circuit (42) configured to estimate a frequency error between the first clock and the second clock based on a change amount of a pointer difference between the write pointer and the readout pointer, and an adjustment circuit (43) configured to output, as an adjustment multiple ΔN, a value obtained by dividing the estimated frequency error by a frequency of the reference clock. The clock generation circuit (44) generates the second clock by multiplying the reference clock by a rational number (N+ΔN) using the adjustment multiple ΔN output from the adjustment circuit (43). A data transfer circuit capable of speeding up clock synchronization can be provided.

A method monitors a sensor clock signal in a sensor unit, which is generated and output for a data transfer between the sensor unit and a control unit with a predefined period duration. A reference clock signal having a predefined reference period duration is received. The sensor clock signal is compared to the reference clock signal. Based on the comparison, a deviation of the current period duration of the sensor clock signal from a target period duration is detected. Based on the detected deviation, a counting pulse or a reset pulse is emitted.

A method of multi-sensor data fusion includes determining a plurality of first data sets using a plurality of sensors, each of the first data sets being associated with a respective one of a plurality of sensor coordinate systems, and each of the sensor coordinate systems being defined in dependence of a respective one of a plurality of mounting positions for the sensors; transforming the first data sets into a plurality of second data sets using a transformation rule, each of the second data sets being associated with a unified coordinate system, the unified coordinate system being defined in dependence of at least one predetermined reference point; and determining at least one fused data set by fusing the second data sets.

A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.

In one embodiment, a network device, includes a network interface port configured to receive data symbols from a network node over a packet data network, at least some of the symbols being included in data packets, and controller circuitry including physical layer (PHY) circuitry, which includes receive PHY pipeline circuitry configured to process the received data symbols, and a counter configured to maintain a counter value indicative of a number of the data symbols in the receive PHY pipeline circuitry.

Synchronizing a pulse position modulation (PPM) signal. A method includes performing a first synchronization operation by receiving a first series of symbols. The symbols in the first series are transmitted with a pulse in a known slot, such that the symbols comprise pulses that are substantially equally spaced in time from adjacent symbols. The first synchronization operation includes identifying when each pulse is received for each of the symbols and using information identifying when each pulse is received for each of the symbols in the first series of symbols to identify symbol and slot boundaries for the pulse position modulation signal. The method further includes performing a second synchronization operation by receiving a second series of symbols transmitted in a known pattern, and identifying the known pattern in the received second series of symbols to identify a frame boundary.

[Problem] To determine a time difference between clocks which, for example, are placed far apart from each other with high accuracy at low cost. [Solution] In a time comparison system 20, an intermediate station 21 disperses a single optical signal 21c in the spatial region using the optical complex amplitude modulation to simultaneously transmit the optical signal 21c to a plurality of comparative stations 22 and 23 apart from each other. The intermediate station 21 transmits the optical signal 21c while changing the transmission angle using phase modulation, performs intensity scanning for the reflected light c1 of the optical signal 21c, and detects the peak intensity to determine the directions of the comparative stations 22 and 23. The reflected light c1 of the optical signal 21c transmitted to the comparative stations 22 and 23 of which the direction have been determined, is detected to determine a round-trip propagation delay time between the intermediate station 21 and each of the comparative stations 22 and 23. The difference calculation unit 25 calculates a sum of time difference between each of times to and tb associated with the comparative stations 22 and 23 and the time tc associated with the intermediate station 21, and the determined propagation delay time to determine time information of each of the comparative stations 22 and 23. Based on the result of subtracting, from the time information of the comparative stations 22, the time information of the comparative stations 23, the time difference between the comparative stations 22 and 23 is determined.

The present invention relates to the field of digital signal processing, and in particular to a Costas sequence time-frequency joint synchronization method based on all-phase spectrum correction. The method improves the defects existing in a discrete frequency spectrum correction algorithm using short-time Fourier transform and sliding correlation. The improvement mainly comprises: the present disclosure provides a solution based on iterative optimization: when an actual frequency offset is an integral multiple of the spectral resolution, a large error can occur, frequency offset correction and time delay correction are carried out on a signal by using an estimated value having a large estimated error, then estimation is carried out again, and the frequency offset of the signal is not a special value by means of an iteration mode.

A system for synchronizing a local audio processing clock rate of a digital signal processor (DSP) to an audio clock rate of a network to which the DSP is connected. The system includes an adjustable clock synthesizer that is configured to establish the local audio processing clock rate of the DSP. The DSP is configured to generate events that are associated with the local audio processing clock rate of the DSP. The DSP is further configured to monitor the generated events over time and based on the monitored events cause the adjustable clock synthesizer to adjust the local audio processing clock rate of the DSP to better match the network audio clock rate.

A physical layer transceiver and a network node including the transceiver. The transceiver includes a media independent interface, a converter circuit block comprising circuitry configured to convert digital signals to analog signals for transmission over a network communications medium and convert analog signals received over the medium to digital signals, and one or more processing blocks configured to process digital data communicated between the media independent interface and the converter circuit block according to a network protocol. Management and control circuitry including power management circuitry and reset circuitry are provided. The transceiver further includes at least one single event effect (SEE) monitor, such as an ambience monitor, a configuration register monitor, a state machine monitor, or a phase locked loop (PLL) lock monitor, configured to detect and respond to an SEE event in the transceiver.