Integrated circuit (IC) static random-access memory (SRAM) comprising pass-gate transistors and pull-down transistors having different threshold voltages (V.sub.t). A pass-gate transistor with a higher V.sub.t than the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a different amount of a dipole dopant source material is deposited as part of the gate insulator for the pull-down transistor than for the pass-gate transistor, reducing the V.sub.t of the pull-down transistor accordingly. In some examples, an N-dipole dopant source material is removed from the pass-gate transistor prior to a drive/activation anneal is performed. After drive/activation, the N-dipole dopant source material may be removed from the pull-down transistor and a same gate metal deposited over both the pass-gate and pull-down transistors.

Integrated circuit (IC) static random-access memory (SRAM) bit-cell structures comprising pass-gate transistors having a different number of active channel regions than the number of active channel regions in pull-down transistors. A pass-gate transistor with fewer active channel regions than a pull-down transistor may reduce read instability of an SRAM bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, one or more pass-gate transistor channel regions are impurity doped or removed from either a top side or bottom side of the pass-gate transistors to depopulate the number of active channel regions relative to a pull-down transistor.

Integrated circuit (IC) static random-access memory (SRAM) comprising colinear pass-gate transistors and pull-down transistors having different nanoribbon widths. A narrower ribbon width within the pass-gate transistor, relative to the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a transition between narrower and width ribbon widths is symmetrical about a centerline shared by ribbons of both the access and pull-down transistors. In some examples, the ribbon width transition is positioned within an impurity-doped semiconductor region shared by the access and pull-down transistors and may be located under a terminal contact metallization. In some examples, the impurity-doped semiconductor regions surrounding the ribbons of differing width also have differing widths.

The present disclosure relates to semiconductor structures and, more particularly, to SRAM bit cells and methods of manufacture. The structure includes a p-FET gate structure including p-FET work function material and an n-FET gate structure including the p-FET work function material. Alternatively, the p-FET gate structure includes n-FET work function material, and the n-FET gate structure includes p-FET work function material.

Stitched dies having a cooling structure are described. For example, an integrated circuit structure includes a first die including a first device layer and a first plurality of metallization layers over the first device layer. The integrated circuit structure also includes a second die including a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the second die by a scribe region. A common conductive interconnection is coupling the first die and the second die at a first side of the first and second dies. A plurality of microfluidic channels is coupled to the first side of the first and second dies.

A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.

The present invention provides a layout pattern of static random access memory, comprising a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

A semiconductor device, including: a first memory cell including a first transistor; a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor self-aligned to the first transistor; and a plurality of junctionless transistors, where at least one of the junctionless transistors controls access to at least one of the memory cells.

A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.

A semiconductor device including a substrate; first to third active patterns on an upper portion of the substrate, the active patterns being sequentially arranged in a first direction and extending in a second direction crossing the first direction; first to third power rails respectively connected to the first to third active patterns, wherein a width of the second active pattern in the first direction is at least two times a width of the first active pattern in the first direction and is at least two times a width of the third active pattern in the first direction, the first active pattern is not vertically overlapped with the first power rail, the second active pattern is vertically overlapped with the second power rail, and the third active pattern is not vertically overlapped with the third power rail.